Dear NXP supporter:
Development enviroment of the project is:S32DS_Power_v2017.R1, PE multilink universal
Simple project introduction: Core0 and Core1 are configured in my project, Core0 runs a Safertos system, Core1 runs a simple program without rtos which lights a led in timer interrupt periodically.
The issue is: If safertos program is disabled in Core0, the Core1 operates well(LED blinks periodically).However, if safertos is enabled, the LED of Core1 will stop blinking, it seems like the Core1 is stucked somewhere.
The code is showed below:
Core0:
I have found a clue for reference : if interrupts related to a module in one core are not disabled before initialization, it will result in program exception of other cores.
Could you please give me some hint? thank you in advance.
Thank you again~
It is said that my account is not verified by email, but i can not verified with my email. Coud you help me to handle it？ thank you
very much
Hi,
first, I would try to find out what caused the exception exactly. For example, if you got Program Interrupt (IVOR 6) then you can get following details from core registers:
SRR0 is the most interesting - it points to instruction which caused the error, so it may provide more hints about the root cause. The same table you can find for other exceptions in the reference manual.
Regarding issues with our account, please create new case here:
https://support.nxp.com/s/?language=en_US
Regards,
Lukas
Here is the debug result:
Core0:
The STM interrupt(which is necessary for saferots) is enabled, and safertos system is running well.
Core1:
a IVOR1 error is triggered
lucas,
Thank you very much~
I can not read srr0, because i met some strange problems when debugging dual-core project.
I have done some further test, found that: STM interrupt is configured for Safertos in core0. if i disable the following instruction, other core(core1)can run well.
pusINTCPSRSTMRegAddr is a register addr to configue STM interrupt periority.
So it's no doubt that the issue is caused by interrupt. An interrupt configured in one core will affect other cores.
Could you tell me how to configue interrupt correctly in multicore system?
Thank you!
