Hi,
I have some strange happenings going on.
When I enable a breakpoint in an ISR, the code immediately stops at the breakpoint.
It doesn't seem to be caused by the code, but only because of the breakpoint being set.
I set the breakpoint at random times. Like 3,4,5,6,7 minutes in and it's the same.
Somehow enabling a breakpoint is causing the ISR to be called?
I have a GPIO pin I enable for an interrupt.
SIUL2.MSCR[PC4].R = 0u;
SIUL2.MSCR[PC4].B.IBE = 1u;
SIUL2.IMCR[674-512].B.SSS = 1u;
SIUL2.IFEER0.B.IFEE18 = 1u; /*falling edge event enabled (As per HITS Active Level = Low) */
/* SIUL2.IFER0.B.IFE18 = 1u; */ /*enable interrupt filter */
SIUL2.IRER0.B.EIRE18 = 1u; /*enable interrupt */
void SIUL_EIRQ_C(void)
{
if(SIUL2.ISR0.B.EIF18) /* TP 394 */
{
/* Clear IRQ 18 */
SIUL2.ISR0.B.EIF18 = 1; <-- When I enable breakpoint here, the code stops immediately
WDTC++; <-- Counter is 0.
}
}
Thanks
So, somehow the breakpoint is tied to IRQ 18.
I can set the breakpoint in other parts of the code and whenever I do, only IRQ 18 triggers.
I set counters to monitor how many times all the IRQs trigger. When I break in other parts of the program,
I only see the IRQ 18 counter increase.
So it doesn't matter where the break point is set, I just know that each time the breakpoint is set, IRQ 18 triggers.
Thanks,
Hi Martin,
I went back and setup ISRs for SIUL_EIRQ_0_7, SIUL_EIRQ_8_15 and SIUL_EIRQ_24_31.
None of the other ISRs have a problem. It only seems to happen with SIUL_EIRQ_16_23.
I changed the ISR names in hopes something would change, but nothing did.
(uint32_t) &SIUL_EIRQ_0_7, /* Vector # 243 SIUL EIRQ [0-7] - SIUL Combined External Interrupt */
(uint32_t) &SIUL_EIRQ_8_15, /* Vector # 244 SIUL EIRQ [8-15] - SIUL Combined External Interrupt */
(uint32_t) &SIUL_EIRQ_16_23, /* Vector # 245 SIUL EIRQ [16-23] - SIUL Combined External Interrupt */
(uint32_t) &SIUL_EIRQ_24_31, /* Vector # 246 SIUL EIRQ [24-31] - SIUL Combined External Interrupt */
Also, it doesn't matter where I add the breakpoint.
void SIUL_EIRQ_16_23(void)
{
if(SIUL2.ISR0.B.EIF18) /* TP 394 */
{
/* Clear IRQ 18 */
SIUL2.ISR0.B.EIF18 = 1;
WDTC++;
}
}