Hi Sandrine,
The IPF ensures that only valid input pin transitions are received by the eMIOS Channel edge detector. The IPF is enabled by EMIOS_CHx.CCR[IF] field, configuring the filter latency.
In fact filter latency represents minimum pulse width which can pass the filter. Input signal is sampled on clock edge of selected clock(I guess rising edge); suppose minimum IF[0:3] = 0x0001 (meaning minimum pulse width of 2 filter clock periods), then if input signal is stable for 3 clock edges, the input signal propagates through filter.
FCK selects a clock for IPF; Prescaled clock means clock after channel prescaler, so you need to include both the global and channel prescaler into a calculation. Moreover the channel prescaler have to be enabled by UCPREN bit. The Main clock means the peripheral clock.
So if you have for example IF = 0b1000, FCK = 0, GPRE = 7, peripheral clock is 60Mhz then the minimum pulse width, which pass the filter should be
Width = (FLT_CLK periods+1) / [60Mhz/(GPRE+1)/(UCPRE+1)]
Thus for example for UCPREN=1 and UCPRE=0
Width = (16+1) / [60Mhz/(7+1)/ (0+1)] = 2.7us
BR, Petr
