MPC5604 I2C Interface Usage Model

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MPC5604 I2C Interface Usage Model

Contributor I

I'm currently working on an MPC5604 project that uses the embedded I2C interface as a master.  From the hardware documentation (I'm waiting for the prototype) it looks like the I2C interface, when acting as a receiver, requires the driver set the next bytes acknowledge state (in IBCR.NOACK) before reading the data register and that reading the data register starts the next bytes transfer.  If true this has the unfortunate effect of making the driver decide whether it wants to receive the byte after next before it can even examine the current byte.  Ideally, the driver would be able to examine and process the current byte before its acknowledge.  Of course I could be misinterpreting the documentation, in which case ignore this.




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NXP TechSupport
NXP TechSupport


Yes, that is true.

However in master receive mode the reading the data register does not start data transfer. It just initiates next byte data receiving. The slave is transmitting the data. Moreover in master receive mode reading the IBDR will return the last byte received.

So if a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (TXAK) before reading the 2nd last byte of data. This read initiates next byte (last) data receiving. In this case the slave transmits the byte (last) which is not acknowledged by master.

In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the next byte of data. Setting RXAK means an 'end of data' signal from the master receiver, after which slave must be switched from transmitter mode to receiver mode by software. A dummy read then releases the SCL line so that the master can generate a STOP signal.