Integrating MPC5777C + AN5191 initialization code in S32DS (gcc) environment

[ricardofranca]

Hello,

I was able to run my MPC5777C with the initialization code provided by AN5191 in the Green Hills environment. Now I am trying to use it with the S32DS environment (gcc + USB Multilink probe) and I added some of the AN5191 code in the default startup.S file so that I could have cacheable internal SRAM and optimized Flash access times. However, I am unable to port the code that locks the stack in the data cache and I am unable to debug it because all breakpoints I try to include in _start() are ignored (I can debug starting from main(), when it is already too late).

- How can I debug _start()?

- Is there any available port of the AN5191 code and linker directives to gcc?

Thanks!

Ricardo

[davidtosenovjan]

It should not be a problem to debug from a start as debugger stops at first instruction.

I have example code that is however based on GHS as well:
https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5777C-PinToggleStationery-GHS714/ta-p...

A colleague ported it to S32DS, but I am not sure what exactly has been used:
https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/Example-MPC5777C-Single-ELF-multi-core...

[ricardofranca]

Hello David,

I finally figured out that my "Release" configuration was missing -g3 flag for the assembler, then the debugger skipped my .S files. Having fixed that, I was able to debug _start. I ended up replacing the startup code of the single-ELF-multi-core example with something that looked (even more) like the AN5191 and everything seems to be working fine.

By the way: Is there any performance difference between a single core of MPC5777C and a MPC5674F if both run at 264MHz? When I ran some code in the NXP development kits for these MCUs, it seemed 5674F was slightly faster.

Thanks,

Ricardo

[davidtosenovjan · Accepted solution]

Yes, there is a difference caused by e2eECC. Single-beat accesses to RAM will take 2 additional clock cycles due to e2eECC which cannot be bypassed. This is mitigated only by cache and write-buffer contributions.

Isolated random accesses to un-cached memory may be a bit slower (but safer as MPC5777C is ASIL-D compliant).