I'm using 2 cores (both z4) of the MPC, where each core uses some peripherals. However all interrupt vectors are configured to be executed on core1. When I initialize for example the SPI5 peripheral on core1, the PSR342 shows that the interrupt is sent to both cores. During initialization the default (core0 target) bit is not cleared, only the core1 target is added.
What is the recommended way to prevent this? I know I can remove the core0 target manually, but maybe there is a nicer solution? I'm using SDK RTM 2.0.0
The INTC peripheral is designed to work like this: the reset value of the INTC_PSRn->PRC_SELN0 bitfield is 1, so all interrupts are enabled for core0 by default. Unfortunately, in SDK PA RTM 2.0.0 there is no way to automatically prevent this. You can only manually disable the interrupt for core0 before enabling the peripheral. This behavior is shown in the interrupt_control_multicore example.
However, the interrupt_manager driver has been recently rewritten and this issue is no longer present. When calling INT_SYS_EnableIRQ(irqNum), the driver will enable irqNum only for the current core and disable it for other cores. This feature should be included in the future SDK PA releases.