Flash ECC and EDC error

[Jamber_H]

Hi,

I am confused about Flash ECC and EDC error.

I think EDC error means any uncorrectable ECC error, such as 2-bit error or multi-bit error. In UTEST, there are 3 areas used for EDC/ECC, single-bit ECC, double-bit ECC, EDC after ECC. Does "EDC after ECC" mean it generate an ECC error firstly then generate an EDC error? If so, does "double-bit ECC" generate EDC? If not, why?

In this figure, double-bit ECC area not generate an EDC error, and EDC after ECC area not generate an ECC error, I want to know why.

Best regards

Jamber

[davidtosenovjan]

Hi, it is a bit otherwise.

"EDC after ECC" is another safety mechanism implemented in the flash memory its primary intention is to detect failure in ECC logic.

Reading of data pattern stored on data address 0x00400080 invokes only FCCU fault NCF[34], nothing else (it returns valid data 0xFFFFFFFF to the CPU). It simulates situation when "EDC after ECC" mechanism detects a hidden failure.

In real case when flash data are massively corrupted, in may happen multiple fault reaction happens simultaneusly (NCF[21-23] and NCF[34]).

But this picture is related to UTEST test patterns.

[Jamber_H]

Hi, David

Thanks for your reply. So can I think that EDC error is generated when flash has error but not trigger an ECC error?

Best regards

Jamber

[davidtosenovjan · Accepted solution]

In this case (error pattern at 0x00400080) it would be so.