I3C SDA and SCL pin configured for Pullup Enabled, but output stays low

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I3C SDA and SCL pin configured for Pullup Enabled, but output stays low

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aberger
Contributor V

I am using the FRDM-MCXA153 board and have routed I3C0_SDA to pin 2  (Port1, Pin8) and I3C0_SCL to pin 3 (Port1, Pin9). Using Config Tools, I have configured the SDA and SCL pins as follow

Slew Rate = Fast
Open Drain = Enabled
Drive Strength = Low
Drive Strength 1 = Normal
Pull select = Pullup
Pull enable = Enabled
Passive filter = Disabled
(and for SDA, Pull value = Low)

(Generated code in pin_mux.c for I3C0_SDA is shown below)

 

 

 /* PORT1_8 (pin 2) is configured as I3C0_SDA */
    PORT_SetPinMux(BOARD_INITPINS_BMS2_SDA_PORT, BOARD_INITPINS_BMS2_SDA_PIN, kPORT_MuxAlt10);

    PORT1->PCR[8] =
        ((PORT1->PCR[8] &
          /* Mask bits to zero which are setting */
          (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_PV_MASK | PORT_PCR_ODE_MASK | PORT_PCR_IBE_MASK)))

         /* Pull Select: Enables internal pullup resistor. */
         | PORT_PCR_PS(PCR_PS_ps1)

         /* Pull Enable: Enables. */
         | PORT_PCR_PE(PCR_PE_pe1)

         /* Pull Value: Low. */
         | PORT_PCR_PV(PCR_PV_pv0)

         /* Open Drain Enable: Enables. */
         | PORT_PCR_ODE(PCR_ODE_ode1)

         /* Input Buffer Enable: Enables. */
         | PORT_PCR_IBE(PCR_IBE_ibe1));

 

 

I can view the peripheral register at runtime and see that both pins are configured as expected:

aberger_1-1722357571195.png

However, the pin outputs remain low. (I am measuring the voltage levels on the Arduino Header J2-20 and J2-18 on the demo board). 

I am trying to use the I3C peripheral to communicate with I2C devices, so the following I3C Initialization routine runs after BOARD_InitPins() is called in my main():

 

#include "fsl_i3c.h"

#define I2C_BAUD_HZ 100000U
#define I3C_PPBAUD_HZ 4000000U

void I3cKinetis::Configure(void) 
{
    uint32_t clockFreqHz = CLOCK_GetFreq(kCLOCK_CoreSysClk); // 96 MHz

    i3c_master_config_t fslConfig;
    I3C_MasterGetDefaultConfig(&fslConfig);

    // Configure for I2C
    fslConfig.disableTimeout = true;
    fslConfig.hKeep = kI3C_MasterPassiveSDASCL;
    fslConfig.enableOpenDrainHigh = false;
    fslConfig.enableOpenDrainStop = true;
    fslConfig.baudRate_Hz.i2cBaud = I2C_BAUD_HZ ;
    // For now, just use the i2c baudrate for opendrain baudrate
    fslConfig.baudRate_Hz.i3cOpenDrainBaud = I2C_BAUD_HZ ;
    // but the Push-Pull baudrate is given by
    // clockFreqHz/(2*(PPBAUD + 1).
    // where PPBAUD must be an integer between [0, 15].
    // So the Push-Pull baudrate can't be slower than
    // clockFreqHz/(2*16)
    fslConfig.baudRate_Hz.i3cPushPullBaud = I3C_PPBAUD_HZ ;

    I3C_MasterInit(I3C0, &fslConfig, clockFreqHz);
}

 

 

Are there extra steps I need to take to configure the I3C pins for open drain, with pull-up?

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HangZhang
NXP Employee
NXP Employee

Hi @aberger 

You can download the MCXA153 SDK from the NXP official website.

Select Board | MCUXpresso SDK Builder (nxp.com)

HangZhang_0-1722415500492.png

In SDK_2_16_000_FRDM-MCXA153\boards\frdmmcxa153\driver_examples\i3c,
there are i3c examples.
there are pin config in the example, you can refer to it.

Hope this will help you.

BR

Hang

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aberger
Contributor V

This isn't actually helpful. I took a look at the "i3c_polling_b2b_transfer_master" example. Even though it claims to first execute a transfer in I2C mode, the pins are not configured for Open Drain (with Pullup Enabled). Without Open Drain, I cannot communicate with a target device that requires support for clock stretching. So my question remains: how to actually get the I3C pins configured for Open Drain, with Pullup Enabled

(I will note that Config Tools did succeed at configuring I2C pins for Open drain, with Pullup Enabled. I don't understand why the same configuration, specified in the routing details for the I3C pins, does not achieve Open Drain behavior). 

aberger_0-1722461739231.png

 

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HangZhang
NXP Employee
NXP Employee

Hi @aberger 

I understand your question.
During pin initialization, there is no need to configure open drain mode. Because this has already been implemented inside the chip, you don't need to worry.
If you want to test the open drain status, you need to test it when transmitting data.

BR

Hang

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