Hi,
I'm developing with the MKL1732ZVFM4, I'm using the I2C0 in VLPR at a 100kHz speed, the core is drive by the LIRC of 8MHz, the core is running at 4MHz and the bus & flash at 1MHz. I've Review the baud generator of the MCUXpresso API & the multiplier and divider of the F register values are updating correctly. What else could be generating the frequency error? The freq espected is of 100kHz & the freq measured by an scope is 90.4kHz
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Hello Daniel,
I have replicated what you mentioned and your statement is correct, I get 90.91 kbits/s. You always get a SCL signal below 100 kbits/s. This is caused by the SCL low and high times as this are not the same.
The speed grades (let's say standard mode: 100 kbits/s) are maximum ratings and it is likely that the master will produce a lower speed on the bus due to resistors, capacitance, SCL hold times, etc.
In fact, it is recommended to keep the baudrate below the maximum to allow system to operate successfully.
I recommend you to read the following article from I2C spec about clock speed.
https://www.i2c-bus.org/speed/
I hope it helps!
Have a great day,
Felipe
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Hi Daniel,
Could you please try using baudrate of 50 Kbps? I2C module in VLPR mode has bus clock limited to 1MHz and I2C baudrate should not exceed clock/20.
Hope it helps!
Have a great day,
Felipe
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Hi Felipe,
I've reviewed the system at 50kHz and the frecuency measured with a scope is 99.08% correct.
Also I've reviewed the documentation of I2C & the feeding clock for the I2C peripheral in VLPR is the system clock. In my application the system clock is at 2MHz, so the 100kHz rate for the I2C should be reached.
So I don't know why it reaches only 90.4kHz if the divider is exactly at 1/20, I hope you could help me to solve this.
Kind Regards
Daniel
Hello Daniel,
I have replicated what you mentioned and your statement is correct, I get 90.91 kbits/s. You always get a SCL signal below 100 kbits/s. This is caused by the SCL low and high times as this are not the same.
The speed grades (let's say standard mode: 100 kbits/s) are maximum ratings and it is likely that the master will produce a lower speed on the bus due to resistors, capacitance, SCL hold times, etc.
In fact, it is recommended to keep the baudrate below the maximum to allow system to operate successfully.
I recommend you to read the following article from I2C spec about clock speed.
https://www.i2c-bus.org/speed/
I hope it helps!
Have a great day,
Felipe
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!
- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
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