eDMA component abilities shown on ADC measurement example

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1. Introduction

This tutorial contains the following goals:

1) How to use the main features of the eDMA component 2.4.0 (periodic trigger, peripheral request, linking, scatter-gather) in the Peripherals Configuration Tool.

2) How to set up periodic ADC autonomous (without CPU) queued measurement controlled by DMA.

2. Prerequisites

The application is developed in MCUXpresso IDE 11.5.0 which can be downloaded from https://www.nxp.com/mcuxpresso/ide website. It integrates MCUXpresso Config Tools Version 11 that is used for application design and configuration.

The FRDM-K66F - Freedom Development Platform for Kinetis K66 SDK version 2.11.0 can be downloaded from the https://mcuxpresso.nxp.com/ website or using the MCUXpresso IDE.

3. Application description

3.1. Description

The main goal of this application is to show the configuration of the DMA peripheral which can be used for the ADC channel to be measured and for collecting the results into the resulting output array. It demonstrates an approach for periodic measurement of multiple ADC channels without CPU intervention. It can be used on any MCU with a simple ADC peripheral (without a possibility to queue measured channels).

3.2. Application details

The application starts with the initialization of pins, clocks, and peripherals configured by the MCUXpresso Config Tool. After the initial state is printed to the console, it starts the PIT (periodic interrupt timer). The PIT channel named Trigger causes periodic transfer on the DMA channel named ADC, which configures the ADC peripheral’s channel to be measured. When the timer counting is completed, the ADC measures the analog signal of the DAC peripheral that has been already initialized. The interrupt routine of the PIT Trigger channel includes the actual DAC data reading sequence that will be printed at the end of the console.

After the end of the measurement loop, there is the ADC peripheral’s DMA request which initiates the DMA channel named OUTPUT to read the measured ADC data. The DMA channel OUTPUT links the DMA channel named DAC, which increases the buffer read index of the DAC peripheral and generates the next analog signal to be measured by the ADC. The sample number corresponds to the number of major loops of the DMA channel OUTPUT. The major count completion interrupt of the DMA channel OUTPUT stops the measurement trigger (PIT) and enables the DMA request of the DMA channel named PROCESS. The DMA channel PROCESS processes the whole dataset by sorting it into individual data buffers using the scatter-gather function. The major count completion interrupt of the DMA channel PROCESS sets the flag for printing the results and starts the delay timer (PIT second channel named Delay) that delays individual measurements. The post-delay interrupt routine stops the PIT Delay channel and restarts the PIT Trigger channel, which initiates the whole cycle again.

Figure 1. Application diagram

4. MCUXpresso Config Tool configuration

The project includes the initial configuration of the following peripherals by the Peripherals Tool:

DAC (Digital to Analog Converter)
ADC (Analog to Digital Converter)
PIT (Periodic Interrupt Timer)
eDMA (Enhanced Direct Memory Access)

4.1. DAC peripheral

The DAC peripheral is used for creating simulated data to be measured by the ADC.

DAC peripheral setup:

Mode – Buffered
DAC reference voltage – DACREF_2 – the same voltage reference as for ADC, so that both peripherals are in the same voltage ranges.
Enable DAC – true
Enable DAC buffer - true
Trigger mode – Software trigger (configured by DMA write to register C0, corresponds to the dac_trigger[] configuration)
Work mode – Swing mode (demonstration choice)
Data buffer values – 10 demonstrations of values from 100 to 1000 with step 100
Buffer read index - 0

The DAC buffer works in swing mode, so it moves the buffer read index from the first item to the last, then back to the first, and so on. After the one loop is measured by the ADC nearly the same values are printed out to the console log, due to the same voltage reference selected in both the DAC and the ADC. The DAC interrupt is not used.

Figure 2. DAC Configuration

4.2. ADC peripheral

The ADC peripheral is used for measuring an analog signal (in this case, generated by the DAC peripheral) and converting it into a digital signal.

ADC peripheral setup:

Reference voltage source – VrefH/VrefL
Input clock source – Bus clock divided by 2.
Asynchronous clock output – false
Divide input clock source – by 8 (to achieve better accuracy)
Sample resolution mode – Single-end 12-bit (the same as DAC resolution)
Perform auto-calibration – true (to achieve better accuracy)
Use hardware trigger – false
DMA requests – true

The ADC channel selection is configured by the DMA. The adc_trigger[] array includes configurations of the SC1A register, which selects and triggers the ADC channel measurement.

The clock frequency for the ADC measurement is set to 3.75 MHz. The conversion time is calculated in the following way:

Conversion time = SFC adder + AverageNum * (BCT + LST adder + HSC adder)

Where:

SFC adder (Single or First Continuous time adder): 5 ADCK + 5 bus clock cycles
AverageNum (Average Number factor): 8
BCT (Base Conversion Time: for 12-bit single-ended): 20 ADCK
LST adder (Long Sample Time adder): 0 ADCK
HSC adder (High-Speed Conversion time adder): 0 ADCK
ADCK (ADC clock cycle period): (16/60000000) s

The resulting conversion time is calculated as follows:

Conversion time = (5 ADCK + 5 bus clock cycles) + 8 * (20 ADCK + 0 ADCK + 0 ADCK)

= 165 * 16/60000000 + 5/60000000

= 44.083 us

Figure 3. ADC configuration

4.3. PIT peripheral

The PIT peripheral is used for setting time delays.

PIT peripheral setup:

Run PIT in debug mode – true (application is demonstrated in debug mode)
Clock source frequency – 60 MHz

PIT Channel 0 is configured to set the delay between each ADC measurement. It periodically triggers a DMA transfer of DMA channel 0 which writes to the ADC register SC1A.

Setup PIT channel 0:

Channel ID – Trigger (optional identifier)
Channel number – 0 (corresponds to the DMA channel number)
Channel period – 60 us (the period must be higher than the calculated ADC conversion time 44.083 us and DAC value stabilization)
Interrupt – true
Interrupt request – Enabled in the initialization

Figure 4. PIT configuration channel 0 named Trigger

PIT Channel 1 is configured to set a delay for printing results. It starts at the end of the measurement loop.

PIT channel 1 setup:

Channel ID – Delay (optional identifier)
Channel number – 1
Channel period – 10 s (period of the whole measurement loop)
Interrupt – true
Interrupt request – Enabled in the initialization

Figure 5. DMA channel OUTPUT TCD configuration

4.4. eDMA peripheral

The eDMA peripheral component initializes the DMA and DMAMUX (DMA request multiplexer) peripherals. The DMA controller enables moving data from one memory-mapped location to another without CPU involvement.

Note: The error interrupt vector and channel error event for all DMA channels are enabled. It can improve the debugging process. The ISR is defined in the DMA_ERROR handler.

eDMA peripheral setup:

Priority arbitration mode – Round-robin (no specific channel priorities were set because channels are not used simultaneously)
Debug mode enable – true (application is demonstrated in debug mode)

Figure 6. General eDMA configuration overview

The application example uses 4 DMA channels for control:

ADC (always-on DMA request triggered by PIT)
DAC (disabled DMA request)
OUTPUT (ADC peripheral DMA request)
PROCESS (always-on DMA request)

All used DMA channels are configured as Non-transactional (TCD structures) channel API mode, which allows you to configure all TCD (Transfer Control Descriptor) registers.

4.4.1. Channel ADC

The eDMA channel ADC (Figure 7) is used for setting and triggering the ADC channel to measure the analog signal generated by the DAC peripheral. It demonstrates the use-case of a triggered always-on DMA request when the selected DMA channel (0) is triggered by the corresponding PIT channel (0). The peripheral request is enabled; therefore, the channel operates immediately after the PIT trigger timer starts and completes counting.

eDMA channel ADC setup:

Channel API mode - Non-transactional (TCD structures)
Channel ID – ADC (optional channel prefix name)
eDMA channel number – 0
eDMA request – AlwaysOn (any always-on request number)
Periodic trigger enable – true (requires initialization of PIT channel 0)
Reset channel – true
Peripheral request enable – true

Figure 7. DMA channel ADC configuration

The Transfer Control Descriptor for the DMA channel ADC (Figure is configured as memory-to-peripheral transfer, which configures the ADC peripheral for measurement.

eDMA channel ADC TCD named ADC_trigger setup:

TCD ID – ADC_trigger

Source address configuration

Data size [Byte] – 4 (one minor loop transfers 4 bytes, which corresponds with the destination register size)
Address expression – &adc_trigger[0] (contains 2 configurations of the ADC0::SC1A register, for demonstration purposes both selected the same ADC channel 23 (0x17) interconnected with the DAC output. The configurations can be different)
External definition – extern uint32_t adc_trigger[];
Offset expression – sizeof(adc_trigger[0]) (SOFF = 4 bytes)
Modulo – Disable modulo

Destination address configuration

Data size [Byte] – 4 (one minor loop transfers 4 bytes, which corresponds to the destination register size)
Address expression – ((uint32_t)(&ADC0_PERIPHERAL->SC1[0])) or (uint32_t)ADC0_PERIPHERAL (it is the first register of the peripheral ADC)
Offset expression – 0 (DOFF = 0 bytes, destination address is always the same – ADC0::SC1A)
Modulo – Disable modulo

Minor loop configuration

Minor loop transfer [Byte] – 4
Minor loop offset – Disabled
Minor loop link enable – false
Bandwidth control – No eDMA engine stalls

Major loop configuration

Major loop count – 2 (MAJOR_LOOP_COUNT – 2 ADC configurations)
Source last address adjustment – -8 (SLAST = (-1) * SOFF * MAJOR_LOOP_COUNT)
Destination last address adjustment – 0 (DLAST = (-1) * DOFF * MAJOR_LOOP_COUNT)
Major loop link enable – false
Auto stop request – false (channel operation is triggered by the hardware – PIT trigger)

Scatter-gather configuration

Scatter-gather enable – false
Constant TCDs - true
Initialize TCD - ADC_trigger

Figure 8. DMA channel ADC TCD configuration

4.4.2. Channel DAC

The DMA channel DAC (Figure 9) is used for setting and triggering the DAC peripheral to generate an analog signal for the ADC measurement. It demonstrates the DMA channel (1) configuration without using a DMA request. A channel without a DMA request can be enabled with a software trigger or with channel linking functionality. In this case, the DMA channel DAC is linked from the DMA channel OUTPUT.

Figure 9. DMA channel DAC configuration

eDMA channel DAC setup:

Channel API mode - Non-transactional (TCD structures)

Channel ID – DAC (optional channel prefix name)
eDMA channel number – 1
eDMA request – DMAMUX disable (without DMA request)
Periodic trigger enable – false
Reset channel – true
Peripheral request enable – false

The TCD for the DMA channel DAC (Figure 10) is configured as a memory-to-peripheral transfer, which configures the DAC peripheral for generating the next analog signal.

eDMA channel DAC TCD named DAC_trigger setup:

TCD ID – DAC_trigger

Source address configuration

Data size [Byte] – 1 (one minor loop transfers 1 byte, which corresponds to the destination register size)
Address expression – &dac_trigger[0] (contains the configuration of the DAC0::C0 register (0xF0) that triggers DAC by software)
External definition – extern uint8_t dac_trigger[];
Offset expression – size of(dac_trigger[0]) (SOFF = 1 bytes)
Modulo – Disable modulo

Destination address configuration

Data size [Byte] – 1 (one minor loop transfers 1 byte which corresponds with the destination register size)
Address expression – ((uint32_t)(&DAC0_PERIPHERAL->C0))
Offset expression – 0 (DOFF = 0 bytes, the destination address is always the same – DAC0::C0)
Modulo – Disable modulo

Minor loop configuration

Minor loop transfer [Byte] – 1
Minor loop offset – Disabled
Minor loop link enable – false
Bandwidth control – No eDMA engine stalls

Major loop configuration

Major loop count – 2 (MAJOR_LOOP_COUNT – 2 ADC configurations)
Source last address adjustment – -1 (SLAST = (-1) * SOFF * MAJOR_LOOP_COUNT)
Destination last address adjustment - 0 (DLAST = (-1) * DOFF * MAJOR_LOOP_COUNT)
Major loop link enable – false
Auto stop request – false (DMA request disabled)

Scatter-gather configuration

Scatter-gather enable – false
Constant TCDs - true
Initialize TCD - DAC_trigger

Note: Instead of the DAC peripheral the DMA channel can send or receive settings to/from any other peripherals that trigger the ADC measurement (for example, a communication peripheral - UART).

Figure 10. DMA channel DAC TCD configuration

4.4.3. Channel OUTPUT

The DMA channel OUTPUT (Figure 11) is used for reading the ADC peripheral results and storing them in memory. It demonstrates the DMA channel (2) configuration using the DMA peripheral request (ADC). The peripheral request is enabled; therefore, the channel operates immediately after the ADC measurement is done.

eDMA channel OUTPUT setup:

Channel API mode - Non-transactional (TCD structures)
Channel ID – OUTPUT (optional channel prefix name)
eDMA channel – 2
eDMA request – ADC0
Enable periodic trigger – false
Enable channel reset - true
Enable peripheral request – true
Asynchronous peripheral request – true

Figure 11. DMA channel OUTPUT configuration

The TCD for the DMA channel OUTPUT (Figure 12) is configured as a peripheral-to-memory transfer which reads the measured values by the ADC peripheral.

eDMA channel OUTPUT TCD named ADC_RESULTS setup:

TCD ID – ADC_RESULTS

Source address configuration

Data size [Byte] – 4 (one minor loop transfers 4 bytes which corresponds to the destination register size)
Address expression – (uint32_t)(&ADC0_PERIPHERAL->R[0]) (reads results from ADC0::RA register)
Offset expression – 0 (SOFF = 0 bytes, the source address is always the same)
Modulo – Disable modulo

Destination address configuration

Data size [Byte] – 4 (one minor loop transfers 1 byte which corresponds to the destination register size)
Address expression – &adc_results[0]
External definition – extern uint32_t adc_results[];
Offset expression – sizeof(adc_results[0]) (DOFF = 4 bytes)
Modulo – Disable modulo

Minor loop configuration

Minor loop transfer [Byte] – 4
Minor loop offset – Disabled
Minor loop link enable – true
Linked minor loop channel – 1(DAC) (every minor loop eDMA channel DAC is linked which triggers the DAC and increases the buffer index that changes the DAC output value)
Bandwidth control – No eDMA engine stalls

Major loop configuration

Major loop count – 20 (MAJOR_LOOP_COUNT – 20 measured samples)
Source last address adjustment – -0 (SLAST = (-1) * SOFF * MAJOR_LOOP_COUNT)
Destination last address adjustment - -80 (DLAST = (-1) * DOFF * MAJOR_LOOP_COUNT)
Major loop link enable – true
Linked major loop channel – 1(DAC) (last minor loop increases the DAC buffer index for the next measurement cycle)
Auto stop request – false

Scatter-gather configuration

Enable scatter-gather – false

Interrupt configuration

Interrupt sources – Major count completion (After the measurement cycle, the interrupt DMA_OUTPUT is invoked. The ISR clears the status flags of the DMA channel OUTPUT channel, stops the PIT trigger timer, and enables the peripheral request of the DMA channel PROCESS. This way, it initiates the next operation.)
Constant TCDs - true
Initialize TCD – ADC_RESULTS
- Enable channel interrupt – true
- Interrupt request – Enabled in initialization
- Enable custom handler name - true
- Interrupt handler name – DMA_OUTPUT

Figure 12. DMA channel OUTPUT TCD configuration

4.4.4. Channel PROCESS

The DMA channel PROCESS (Figure 13) is used for processing the results and storing them in memory. It demonstrates the DMA channel (3) configuration using a DMA always-on request. The peripheral request is disabled; therefore, the channel operates after the request is enabled by the software. In the example application, the DMA request is enabled in the interrupt routine of the DMA channel OUTPUT which is invoked after all major loops transfers are completed (measurement finished). After this DMA transfer, there are two arrays of results, one for each ADC configuration, see configuration array adc_trigger[].

eDMA channel PROCESS setup:

Channel API mode - Non-transactional (TCD structures)
Channel ID – PROCESS (optional channel prefix name)
eDMA channel – 3
eDMA request – AlwaysOn (any always-on request number)
Periodic trigger enable – false
Reset channel – true
Peripheral request enable – false

Figure 13. DMA channel PROCESS configuration

The DMA channel PROCESS contains pre-configured TCDs as memory-to-memory transfers that process the measured data using scatter-gather functionality. In the example application, the data from one source data-array adc_results[] is scattered into two destination data-arrays, data0[], and data1[]. The DMA channel ADC contains two ADC configurations to be measured. The values measured by the first ADC channel configuration are stored into the data0, and after that, the second ADC channel configuration data into the data1.

eDMA channel TCD Data0 setup:

TCD ID – Data0

Source address configuration

Data size [Byte] – 4 (sample size)
Address expression – &adc_results[0] (first sample)
Offset expression – 2*sizeof(adc_results[0]) (SOFF = 8 bytes, read every second sample)
Modulo – Disable modulo

Destination address configuration

Data size [Byte] – 4
Address expression – &data0[0]
External definition – extern uint32_t data0[];
Offset expression – sizeof(data0[0]) (DOFF = 4 bytes)
Modulo – Disable modulo

Minor loop configuration

Minor loop transfer [Byte] – 4
Minor loop offset – Disabled
Minor loop link enable – false
Bandwidth control – No eDMA engine stalls

Major loop configuration

Major loop counts – 10 (MAJOR_LOOP_COUNT – 10 samples)
Source last address adjustment – -80 (SLAST = (-1) * SOFF * MAJOR_LOOP_COUNT)
Destination last address adjustment – Disabled due to scatter-gather mode
Major loop link enable – false
Auto stop request – false (always-on request still enabled)

Scatter-gather configuration

Enable scatter-gather – true
Scatter-gather TCD address – Data1

Setup eDMA channel TCD Data1:

TCD ID – Data1

Source address configuration

Data size [Byte] – 4 (sample size)
Address expression – &adc_results[1] (second sample)
Offset expression – 2*sizeof(adc_results[0]) (SOFF = 8 bytes, read every second sample)
Modulo – Disable modulo

Destination address configuration

Data size [Byte] – 4
Address expression – &data1[0]
External definition – extern uint32_t data1[];
Offset expression – sizeof(data1[0]) (DOFF = 4 bytes)
Modulo – Disable modulo

Minor loop configuration

Minor loop transfer [Byte] – 4
Minor loop offset – Disabled
Minor loop link enable – false
Bandwidth control – No eDMA engine stalls

Major loop configuration

Major loop counts – 10 (MAJOR_LOOP_COUNT – 10 samples)
Source last address adjustment – -80 (SLAST = (-1) * SOFF * MAJOR_LOOP_COUNT)
Destination last address adjustment – Disabled due to scatter-gather mode
Major loop link enable – false
Auto stop request – true (stops always-on request)

Scatter-gather configuration

Enable scatter-gather – true

Scatter-gather TCD address – Data0

Interrupt configuration

Interrupt sources – Major count completion (After the last major loop of the TCD Data1, the interrupt DMA_PROCESS is invoked. The ISR clears the status flags of the DMA channel PROCESS channel, sets the print flag, and starts the PIT delay timer. The results are printed in the console.)
Constant TCDs - true
Initialize TCD – Data0
Enable channel interrupt – true
- Interrupt request – Enabled in initialization
- Enable custom handler name - true
- Interrupt handler name – DMA_DATA_PROCESSED

Figure 14. DMA channel PROCESS TCD configuration Data0

Figure 15. DMA channel PROCESS TCD configuration Data1

5. Application design

Global variables and definitions:

Definitions:
•	SAMPLE_COUNT - number of the measured values from one measurement loop – one swing through DAC buffer (10 values) to top and back => 2 * 10
•	DATA_COUNT - number of the data in each separated output array
•	ADC_CONFIGURATIONS - number of values (channel settings) for ADC0_SC1A register
•	DAC_TRIGGER_CONFIGURATIONS - number of values (SW trigger) for DAC0_C0 register
 
Main global variables:
•	dac_output - Result buffer with DAC output, the array of DAC values filled from the actual pointed buffer index – used for printing purposes/* Result buffer with ADC measurement output - interleaved channels measured data, one by one */
AT_NONCACHEABLE_SECTION_INIT(uint32_t adc_results[SAMPLE_COUNT]) = {0};
/* Process data buffers – output separated measured data from the two selected ADC channels into these two arrays */
AT_NONCACHEABLE_SECTION_INIT(uint32_t data0[DATA_COUNT]) = {0};
AT_NONCACHEABLE_SECTION_INIT(uint32_t data1[DATA_COUNT]) = {0};
/* ADC channel selection: twice channel 23 configuration – 0x17; here you can specify your own channels numbers when you transform the tutorial to real application */
AT_NONCACHEABLE_SECTION_INIT(uint32_t adc_trigger[ADC_CONFIGURATIONS]) = {0x17, 0x17};
/* Set DAC software trigger configuration – 0xF0 */
AT_NONCACHEABLE_SECTION_INIT(uint8_t dac_trigger[DAC_TRIGGER_CONFIGURATIONS]) = {0xF0};

Functions and interrupt handler's description:
int main(void) {
/* Initialization of MCU (pins, clocks and peripherals) */
.
.
.
/* Start the DMA trigger */
    PIT_StartTimer(PIT_PERIPHERAL, PIT_TRIGGER);
/* Inside infinite loop */
if(printFlag){
        	printBuffers();
      }
}

/* PIT0_IRQn interrupt handler */
void PIT_TRIGGER_IRQHANDLER(void) {
/* After each ADC trigger */
/* Fill dac_output array by the actual value */
}

/* PIT1_IRQn interrupt handler */
void PIT_DELAY_IRQHANDLER(void) {
/* At the end of the measurement loop after printing out */
/* Stop delay timer */
  PIT_StopTimer(PIT_PERIPHERAL, PIT_DELAY);
/* Start triggering in the next measurement loop */
  PIT_StartTimer(PIT_PERIPHERAL, PIT_TRIGGER);
}

/* DMA2_DMA18_IRQn interrupt handler */
void DMA_OUTPUT(void) {
  /* After all measurement results in actual loop is transferred by DMA to  adc_results[] */
  /* Stop DMA trigger */
  PIT_StopTimer(PIT_PERIPHERAL, PIT_TRIGGER);
  /* Enable data process DMA channel request */
  EDMA_EnableChannelRequest(DMA_DMA_BASEADDR, DMA_PROCESS_DMA_CHANNEL);
}

/* DMA3_DMA19_IRQn interrupt handler */
void DMA_DATA_PROCESSED(void) {
/* After finishing separation DMA transfers from adc_results[] to the data0[] and data1[] */
/* Start delay next measurement and results printing */
  PIT_StartTimer(PIT_PERIPHERAL, PIT_DELAY);
}
/* DMA_Error_IRQn interrupt handler */
void DMA_ERROR(void) {
/* Just for sure */
}

void printBuffers() {
/* Printed out the DAC values with ADC measured values for comparison */
}

6. Conclusion

The tutorial shows:

1) How to use the main abilities of the DMA component 2.4.0 (periodic trigger, peripheral request, linking, scatter-gather).

2) How to set up periodic ADC autonomous (without CPU) queued measurement controlled by DMA.