Hello! I'm analyzing data samples acquired with SD-ADC integrated into S32R274 AFE block.
I'm using different oversampling ratio settings in AFE_FILTCTRL registers: OSR=0,1,2,3 and USE14=1. My input signal is analog noise or low frequency sinus (trying both).
For every mentioned configuration I get samples with values differs between each other on 512. As I understand, effective 14bit are shifted to fed 16bit SDMA words, so I should keeping this in the mind, divide these value on 2^2=4. So, minimal difference between sample values is 128 (2^7). It means that effective ADC resolution is (14-7)=7, what differs from specified in datasheet.
What I'm doing wrong and how I can to achieve full 14(12) bit resolution with SD ADC?
Also I have an issue with some kind of digital limiting of the signal. I haven't OVERVOLTAGE bits asserted but it looks like some internal circuits are cropped most significant bits from the sample value before SDMA transfer. Probably it happenes while accumulation in decimation block. How I can avoid such behavior or at least to get to know what limiting happened (for example like OVERVOLTAGE bits)? Please look to the attached image to understand what I mean.