I set the RCW of lx2160a
SRDS_PRTCL_S1=8
SRDS_PLL_PD_PLL1=1
SRDS_REFCLKF_DIS_S1=1
but only use serdes 1's XFI.3 XFI.9 XFI.10 (Lane0 Lane6 Lane7)
want to power down Lane1 Lane2 Lane3 Lane4 Lane5 of serdes 1
which register can be controled to power down Lane1 Lane2 Lane3 Lane4 Lane5
Thanks
解決済! 解決策の投稿を見る。
Please refer to the QorIQ LX2160A Reference Manual, Rev. 0, 26.10.2 Unused Lanes
Unused lanes should be powered down to save power and avoid noise on adjacent lanes.
Power down the Rx portion of the lanes by setting LNmRRSTCTL[STP_REQ]=1, waiting for STP_REQ to clear, and then LNmRRSTCTL[DIS]=1.
Power down the Tx portion of the lanes by setting LNmTRSTCTL[STP_REQ]=1, waiting for STP_REQ to clear, and then LNmTRSTCTL[DIS]=1.
//power down serdes 1 lane 1 2 3 4 5
u32 srds1_base_addr = 0x1EA0000;
int lane = 1;
u32 val, tmp;
for(lane=1; lane<6; lane++)
{
tmp = readl(srds1_base_addr + 0x820 + 0x100*lane);
val = 0x5000000;
val = val | tmp;
writel(val, srds1_base_addr + 0x820 + 0x100*lane);
writel(val, srds1_base_addr + 0x820 + 0x100*lane);
tmp = readl(srds1_base_addr + 0x840 + 0x100*lane);
val = 0x5000000;
val = val | tmp;
writel(val, srds1_base_addr + 0x840 + 0x100*lane);
writel(val, srds1_base_addr + 0x840 + 0x100*lane);
}
Please refer to the QorIQ LX2160A Reference Manual, Rev. 0, 26.10.2 Unused Lanes
Unused lanes should be powered down to save power and avoid noise on adjacent lanes.
Power down the Rx portion of the lanes by setting LNmRRSTCTL[STP_REQ]=1, waiting for STP_REQ to clear, and then LNmRRSTCTL[DIS]=1.
Power down the Tx portion of the lanes by setting LNmTRSTCTL[STP_REQ]=1, waiting for STP_REQ to clear, and then LNmTRSTCTL[DIS]=1.
add code in uboot
//power down serdes 1 lane 1 2 3 4 5
u32 srds1_base_addr = 0x1EA0000;
int lane = 1;
u32 val, tmp;
for(lane=1; lane<6; lane++)
{
tmp = readl(srds1_base_addr + 0x820 + 0x100*lane);
val = 0x5000000;
val = val | tmp;
writel(val, srds1_base_addr + 0x820 + 0x100*lane);
writel(val, srds1_base_addr + 0x820 + 0x100*lane);
tmp = readl(srds1_base_addr + 0x840 + 0x100*lane);
val = 0x5000000;
val = val | tmp;
writel(val, srds1_base_addr + 0x840 + 0x100*lane);
writel(val, srds1_base_addr + 0x840 + 0x100*lane);
}