Hi,
we are trying to bringup our custom board with LS1043A by following procedure given in Bringing up layerscape devices using CCS script and DRAM init AN12270.
Due to issue with Flash device , we want to use DRAM boot . As apart of that we have customized ddr4 Init using QCVS Tool and also U-boot complied to target DRAM BOOT.
After run the Lsbp.tcl script. following data is coming in CCS window.
We have verified U-Boot dump in ddr4 by memory view and it was ok. But we are not getting any status on console port. As per the docs from NXP for dram boot, PBL is not required and it will be in bypass mode. Am I correct?.
1. After dumping the U-boot in ddr4, how control will jump to starting address of boot code?
2. As per RCW src console port UART1 is enabled. But we are unable to access it. no prompt is coming on serial port..
3.Please clarify where will be the b problem? or approach is not correct?.
For your reference copy of customized Lsbp.tcl is given below.
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# Script to init ddr, copy u-boot and launch it
namespace eval lsbp {
proc lsbp {} {
#1: Customize the ddr init script file name
source ddr-init-ls1043rdb_pd.tcl
#2: Set device, currently supports ls1021a/ls1043a/ls1046a
set device ls1043a
switch -exact $device {
"ls1021a" { set dut ls1020a }
"ls1043a" { set dut ls1043a }
"ls1046a" { set dut ls1043a }
default {echo This device is not supported; return 0}
}
#3: Set hardcode_rcw
# For LS1043A and LS1046A
# 0x9E: DDRCLK is the reference clock for DDR
# 0x9F: DIFF_SYSCLK is the reference clock for DDR
# For LS1021A
# 0x9B: First try value. See RM for more options
set hardcode_rcw 0x9F
#4: Please customize the CWTAP setting, see Apps note for more info
delete all
config cc cwtap:192.168.10.229
ccs::config_chain "$dut dap sap2"
# Call rcw-override procedure
lsbp::rcw-override $dut $hardcode_rcw
# Parse the JTAG to find out the chain position of DAP, SAP2, Boot Core
set tap [lsbp::tap-parse]
set dap [lindex $tap 0]
set sap2 [lindex $tap 1]
set boot_core [lindex $tap 2]
# Call the pbi procedure to write minimal registers
lsbp::pbi $dut $dap
# Call init-ddrc procedure to initialize DDR controller
lsbp::init-ddrc $dap
# Call loadb procedure to load u-boot.bin to DDR address 0x82000000
lsbp::loadb $sap2
# Release the boot core, ARM core 0
ccs::run_core $boot_core
}
proc rcw-override {dut hardcode_rcw} {
ccs::config_template 0 0x1001 5000
ccs::config_template 0 0x1000 1
ccs::write_reg 0 rcw_src $hardcode_rcw
ccs::write_reg 0 rcw11 0x01098800
ccs::reset_to_debug
ccs::config_chain "$dut dap sap2"
display ccs::get_config_chain
}
proc pbi {dut chain_pos} {
if {$dut == "ls1020a"} {
ccs::write_mem $chain_pos 0 0x1ee0200 4 0 0x82000000
} elseif {$dut == "ls1043a"} {
# For both LS1043/LS1046
ccs::write_mem $chain_pos 0 0x1570418 4 0 0x0000009e
ccs::write_mem $chain_pos 0 0x157041c 4 0 0x0000009e
ccs::write_mem $chain_pos 0 0x1570420 4 0 0x0000009e
#ccs::write_mem $chain_pos 0 0x1570188 4 0 0x80000000
ccs::write_mem $chain_pos 0 0x1570600 4 0 0x00000000
ccs::write_mem $chain_pos 0 0x1570604 4 0 0x82000000
} else {
echo This device is not supported;
return 0
}
}
proc loadb { chain_pos } {
ccs::set_max_tck $chain_pos 18000
set fd [open ./u-boot.bin r]
fconfigure $fd -translation binary
set i 0
while 1 {
set data0 [read $fd 8]
set data0h [bin2hex $data0]
set data1 [read $fd 8]
set data1h [bin2hex $data1]
set data2 [read $fd 8]
set data2h [bin2hex $data2]
set data3 [read $fd 8]
set data3h [bin2hex $data3]
ccs::write_mem $chain_pos 0 [format 0x%x [expr 0x82000000+$i]] 8 0 "$data0h $data1h $data2h $data3h"
if { [eof $fd] } break
incr i 32
}
close $fd
}
proc bin2hex {binstr {delim ""}} {
set s ""
set 0x " 0x"
for {set i 0} {$i < [string length $binstr]} {incr i} {
binary scan [string index $binstr $i] H2 cc
set s ${cc}${s}
if { $i == 3 || $i == 7} {
set s ${0x}${s}
}
}
switch [string length $binstr] {
0 { return "0x00000000 0x00000000" }
1 { return "0x00000000 0x000000${s}" }
2 { return "0x00000000 0x0000${s}" }
3 { return "0x00000000 0x00${s}" }
4 { return "0x00000000${s}" }
5 { return "0x000000${s}" }
6 { return "0x0000${s}" }
7 { return "0x00${s}" }
default {
return $s
}
}
}
proc tap-parse {} {
set sap2 0
set dap 0
set sp 0
set dpaa 0
set gpp_cores {}
set chain_pos 0
set children [ccs::get_config_chain]
set tap_num 0
foreach child $children {
set type $child
#echo $type
if {$type == $ccs::core(sap2)} { set sap2 $tap_num
} elseif {$type == $ccs::core(dap)} { set dap $tap_num
} elseif {$type == $ccs::core(CortexA5)} { set sp $tap_num
} elseif {$type == $ccs::core(lsdpaa2)} { set dpaa $tap_num
} elseif {$type == $ccs::core(CortexA53)} { lappend gpp_cores $tap_num
} elseif {$type == $ccs::core(CortexA72)} { lappend gpp_cores $tap_num
} elseif {$type == $ccs::core(CortexA7)} { lappend gpp_cores $tap_num }
incr tap_num
}
set boot_core [lindex $gpp_cores 0]
echo $gpp_cores;
echo boot_core;
return [list $dap $sap2 $boot_core]
}
}
Thanks& regards
