SError interrupt due to LDAXRB instruction when disable cache on ls1046a RDB

[Tonyx]

Hi Experts

My code runs in EL3 on ls1046a RDB in bare mental environment. Here are the focus code after start up.

Step 1: Disable data cache cache, the the sctlr_el3 is changed from 0x00c5183d to 0x00c51839

Step 2: Update a global variable.

Step 3: do {} while (atomic_flag_test_and_set(&gIRQpRrintmutex));

0000000080005a68: adrp x0, 0x8002e000 <__global_locale+120>
0000000080005a6c: add x0, x0, #0x1b8
0000000080005a70: mov w1, #0x1 // #1
0000000080005a74: ldaxrb w2, [x0]

SError interrupt happened in Step 3: when execute "ldaxrb w2, [x0]" as the resister value as below:

ESR_EL3: 0xbf000002

ELR_EL3: 0x0000000080005a74

If not disable cache as in the step 1, the code execute well.

FUNC_START __asm_disable_dcache
isb
mrs x0, sctlr_el3
bfi w0, wzr, #2, #1 // Disables data cache
msr sctlr_el3, x0
isb
ret

[Tonyx]

Try disable I Cache, MMU and invalidate TLB, still not work.

sctlr_el1, sctlr_el2, sctlr_el3 is changed from 0x00c5183d to 0x00c50838

[yipingwang]

Have you tried to disable data cache before you declared the global variable. If yes, please share the results.

[Tonyx]

Not sure about "disable data cache before you declared the global variable".

Since "disable data cache" is at run time and "declared the global variable" is done in a location of a source code file....

[yipingwang]

Try to flush the data cache before you disable it.

[Tonyx]

May be need to flush the case and invalidate TLBs as in the u-boot code

flush_dcache_all();
__asm_invalidate_tlb_all();