I'm working on bringing up a new board design based on the LX2160A SOC. We are using SERDES configuration 1-13-3, and I've been having some issues with bringing up the SGMII.13 and SGMII.14 interfaces on lanes 6 and 7.
We have determined this evening that our issue is being caused by the fact that our SERDES2 PLLS clock source is an external ZL30363 device that has not been programmed yet when the SERDES initialization is happening. As a result, when we get to u-boot, we find SERDES2.PLLSRSTCTL.RST_ERR = 1.
I can manually request SERDES.PLLSRSTCTL.RST_REQ = 1, and then read back and the PLL indicates LOCK=1, and after that, networking on SGMII.14 seems to be working, but I'm left wondering what other initialization issues I might expect from the fact that the 125 MHz clock isn't ready at SERDES initialization time?
Thanks in advance for any help,
Steve Williams
Tarana Wireless, Inc.
