Hello!
We have custom board with a DDR4 memory (DDR4T04G72) connected to a LS1046A and are currently working on the configuration for the DDR-controller. At the moment we're a bit confused about why we do not even get the DDR clock (MCK0/MCK0_B) up and running.
On a previous generation of the same board, with a different DDR4 memory up and running, we can measure the DDR clock as expected.
We understand if NXP cannot support with the specific memory configurations, but we would like to know what are the minimum requirements to get the DDR clock enabled in the DDR-controller of the LS1046A. Is there a minimum set of DDR settings that must be in place before the DDR clock will start when enabling MEM_EN in DDR_SDRAM_CFG, even if the rest of the configuration is not entierly correct yet? And, are there certain things that will make the DDR-controller to "give up" and shut down the DDR clock after it has been started? We are not using and dynamic power management at the moment.
BR
/Eric
