LS1028A RGMII DP83867 configure

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LS1028A RGMII DP83867 configure

852 Views
bwp530
Contributor IV

we use RGMII to connect to DP83867 on our own board. 

How to conifg the RCW and DTS. 

I have a try but it didn't work.

RCW:

 

 

 

...
CLK_OUT_PMUX=2
EC1_SAI4_5_PMUX=0
EC1_SAI3_6_PMUX=0
USB3_CLK_FSEL=39
ENETC_RCW=0
...

 

 

 

DTS:

 

 

&enetc_port1 {
	status = "okay";
	phy-handle = <&rgmii_phy0>;
	phy-connection-type = "rgmii-id";
	external-phy-connection-type = "rgmii-id";
	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		rgmii_phy0: ethernet-phy@0 {
			reg = <0x0>;
			ti,rx-internal-delay = <0x07>;
			ti,tx-internal-delay = <0x0d>;
			ti,fifo-depth = <0x01>;

		};
	};	

};

 

 

 

 

when system boot up, I use this command to get eno1:

 

ifconfig eno1 up

 

 

after I set a static IP:

 

eno1: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 192.168.2.193  netmask 255.255.255.0  broadcast 192.168.2.255
        inet6 fe80::cccd:e7ff:fe91:cd48  prefixlen 64  scopeid 0x20<link>
        ether ce:cd:e7:91:cd:48  txqueuelen 1000  (Ethernet)
        RX packets 726  bytes 167614 (167.6 KB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 0  bytes 0 (0.0 B)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

 

 

It seems like that the eno1 can receive some packet but can't send packets.

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7 Replies

843 Views
bpe
NXP TechSupport
NXP TechSupport




ENETC port 1 does not have it's own MDIO controller, so if your PHY management
interface is connected to LS1028A EMI1_MDC and EMI1_MDIO pins, it's devnode
should be a child of enetc_mdio_pf3. Besides that, according to LS1028A Datasheet,
Note 2 to Table 38, LS1028A RGMII interface does not have internal delays on
it's RGMII data lines, thus 'phy-connection-type = "rgmii-id" ' and
' external-phy-connection-type = "rgmii-id" ' are not valid. Must be "rgmii".
For the PHY node properties, consult at the PHY vendor. Also, I would suggest
following LSDK User Manual Section 8.6.2.3.1 to check that your port1 is properly
recognized and is visible at the expected name.

Hope this helps,
Platon

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811 Views
bwp530
Contributor IV

hi,

how to use the GTX_CLK_125 port, it must be connected to 125MHz clock? the mac can generate this signal internally?

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825 Views
bwp530
Contributor IV

hi, any update? Could you tell me how to configure the GTX_CLK ports to pull-up or pull-down?

@bpe 

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833 Views
bwp530
Contributor IV

hi bpe:

thanks a lot.

According to your information, I change the DTS:

 

&enetc_port1 {
	status = "okay";
	phy-handle = <&rgmii_phy0>;
	phy-connection-type = "rgmii";
	external-phy-connection-type = "rgmii";	

};

&enetc_mdio_pf3 {
	status = "okay";
	rgmii_phy0: ethernet-phy@0 {
		reg = <0x0>;
		ti,rx-internal-delay = <0x07>;
		ti,tx-internal-delay = <0x07>;
		ti,fifo-depth = <0x01>;

	};
}

 

 

And I check the LSDK 8.6.2.3.1:

 

[    3.162903] fsl_enetc 0000:00:00.0: Adding to iommu group 3
[    3.168530] fsl_enetc 0000:00:00.0: device is disabled, skipping
[    3.180264] fsl_enetc 0000:00:00.1: Adding to iommu group 4
[    3.291556] fsl_enetc 0000:00:00.1: enabling device (0400 -> 0402)
[    3.297807] fsl_enetc 0000:00:00.1: no MAC address specified for SI1, using ee:bb:30:62:cf:80
[    3.306366] fsl_enetc 0000:00:00.1: no MAC address specified for SI2, using 56:3f:8b:6d:9c:7b
[    3.315438] fsl_enetc 0000:00:00.1 eth0: ENETC PF driver v1.0
[    3.321296] fsl_enetc 0000:00:00.2: Adding to iommu group 5
[    3.326903] fsl_enetc 0000:00:00.2: device is disabled, skipping
[    3.332971] fsl_enetc 0000:00:00.6: Adding to iommu group 6
[    3.338574] fsl_enetc 0000:00:00.6: device is disabled, skipping
[    3.344682] fsl_enetc_mdio 0000:00:00.3: Adding to iommu group 7
[    3.455551] fsl_enetc_mdio 0000:00:00.3: enabling device (0400 -> 0402)
[    3.468277] fsl_enetc_ptp 0000:00:00.4: Adding to iommu group 8
[    3.474235] fsl_enetc_ptp 0000:00:00.4: enabling device (0404 -> 0406)
[    7.031344] fsl_enetc 0000:00:00.1 eno1: renamed from eth0

 

 

It looks like that the eno1 is OK. Does this mean that the RGMII port is configured correctly?

when I bring up the eno1:

 

[  123.258916] TI DP83867 0000:00:00.3:00: attached PHY driver [TI DP83867] (mii_bus:phy_addr=0000:00:00.3:00, irq=POLL)
[  123.262391] 8021q: adding VLAN 0 to HW filter on device eno1
[  123.262578] fsl_enetc 0000:00:00.1 eno1: Link is Down
[  127.348254] fsl_enetc 0000:00:00.1 eno1: Link is Up - 1Gbps/Full - flow control off
[  127.348311] IPv6: ADDRCONF(NETDEV_CHANGE): eno1: link becomes ready

 

 

But  the eno1 can't still send data. And I can't test any signal on EC1_TXD or EC1_GTX_CLK.  

I have configure the EC1 port in RCW:

 

...
CLK_OUT_PMUX=2
EC1_SAI4_5_PMUX=0
EC1_SAI3_6_PMUX=0
USB3_CLK_FSEL=39
ENETC_RCW=0
...

 

 

if I want to use RGMII,  does is need some PBI command?

Could you give me some ideas?

@bpe 

 

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584 Views
afterdream
Contributor II

hi,

I meet the same question,  can you have solved your problem?

my situation as follows:

the tx_clk=25MHz, and phy link ok

but the tx_en always low, meaning rgmii still cannot send data!!!

 

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576 Views
bwp530
Contributor IV

Hi:

    In my situation, GTX_CLK_125 is not connected to a external CLK port. So tx port didnot work. we redesigned the hardware board. 

570 Views
afterdream
Contributor II

tks, my question solved!

my hareware use port1-rgmii, not port0

so,I need to change the dts, enabling the port1 node

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