LS1021A booting from Parallel NOR

[renaud]

We have a custom board and trying to boot it from  parallel NOR (64MB). I have defined the RCW as follows:

PBI:

#PBI commands

09570200 ffffffff
09570158 00000300
8940007c 21f47300
#Configure Scratch register
09ee0200 10000000
#Configure alternate space
09570158 00001000
#Flush PBL data
096100c0 000FFFFF

#PBL preamble and RCW header
aa55aa55 01ee0100

#enable IFC, disable QSPI and DSPI
0608000a 00000000 00000000 00000000
20000000 08407900 e0025a00 21046000
00000000 00000000 00000000 20038000
00000000 881b1340 00000000 00000000

e0025a00 and all zeros for bits 415 to 442 seems to be  what I need. Still the system does not read the data out of the flash. They should be copied into the OCRAM at address 0x10000000.

Strangely using my ICE and the value e0025a00, I get a bus error but with f0025a00 (which I found in a script) I get some patterns. Could someone confirm my values are correct in the PBI and RCW.

Cheers

[renaud]

We found the reason, we were getting only pattern from the flash (wrong part with supporting a different voltage)

[yipingwang]

According to LS1021ATWR RCW file, the value e0025a00 is correct.

PBI commands should be as the following.

09570200 ffffffff

09ee0200 60100000

09ea085c 00502880

09570158 00000300

09610000 00000000

894008bc 01000000

89400084 00000000

894008bc 00000000

The attached RCW file is used for LS1021ATWR, you could import it in CodeWarrior IDE, then modify the proper fields according to your target board.

[renaud]

09ee0200 60100000

I understand 0x6010000 is where U-boot is located nad 0x60000000 are the RCW. We are not using U-boot. Our image concatenates the PBI + RCW and Pre-boot loader. The load is actually at offset 0x20000 copied by the Pre-Bootloader.

So I need 09ee0200 10000000 so that the PBL is copied to the OCRAM and executed from there.

Done that using SPI NOR.

[renaud]

894008bc 01000000

89400084 00000000

894008bc 00000000

I guess these are the GIC-400 registers. What does that do? Where do you find their descriptions on the ARM website?

[yipingwang · Accepted solution]

/*
* fix the errata A-007815 and A-007997 on ls1021a
* PCIE hotplug related bits with slot capabilities register cleared on LS1021AQDS and LS1021ATWR.
* PCIE read-only-write-enable bit cleard to prevent overwriting read-only registers.
* PCIe1 GEN3_RELATED_OFF register: 0x0340_0084 little endian
* PCIe2 GEN3_RELATED_OFF register: 0x0350_0084 little endian
* ALTCBAR Register (SCFG_ALTCBAR): 0x0157_0158 big endia
* PBL is also big endian block on LS1021A
*/
.pbi
write 0x570158, 0x00000300
flush
awrite 0x4008bc, 0x01000000
awrite 0x400084, 0x00000000
awrite 0x500084, 0x00000000
awrite 0x4008bc, 0x00000000
.end
~