LS1021A-IOT: How to differentiate PORESET and HRESET from software?

[jean-francoisri]

I'm working on a LS1021A-IOT reference board. I'd like to be able, from softwar,e to know whether the last boot was caused by a power-on (PORESET) or something else (HRESET), without using any additional hardware. I've scoured the Reference Manual but coud not find anything conclusive. The closest I could find was the Watchdog Reset Status Register (WDOG1_WRSR), that defines 2 bits:

• TOUT (bit 1) : Timeout. Indicates whether the reset is the result of a WDOG timeout (0 = no, 1 = yes).
• SFTW (bit 0): Software Reset. Indicates whether the reset is the result of a WDOG software reset by asserting SRS bit (0 = no, 1 = yes)

However, this proves to be incorrect, because even after causing a software reset using the Watchdog Control Register (WDOG1_WCR), by clearing SRS (bit 4), neither of TOUT or SFTW were raised. Is there a register in the LS1021A (or some other board component) that I can query to obtain this information?

My final objective is to implement a persistent DRAM, as described in AN4531. In this application note, it was recommended to initialize the DDR controller on power-on, but bypass the initialization on subsequent resets.

[alexander_yakov]

Do you mean you want to use HRESET for "warm" reset? If yes, than this contradicts with our documentation. The following is said in LS1021A Reference Manual, Table 4-1, the description of HRESET_B signal: "For reset assertion to the chip, use only PORESET_B".

As long as we recommend using PORESET_B for reset assertion to the chip, this means PORESET_B is expected to be used for both power-on reset and "warm" reset, and therefore there is no way to determine reset type by reading the state of any internal register, because all register states will be the same after power-on reset and "warm" reset.

HRESET can be used as input (asserted externally) only if external device wants "to stall/hold the reset sequence" (Table 4-3).

Have a great day,
Alexander

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