How to adjust eye diagram parameters for serdes lanes configured as pcie interface?

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How to adjust eye diagram parameters for serdes lanes configured as pcie interface?

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QiujuYe
Contributor III

Hi,

 

The serdes2 lane E,F,G,H on ls2088A/LS2084A are configured as a 5G pcie interface, but the signal is not good. We adjust the eye diagram parameters,LNxTECR0 [AMP_RED], LNxTECR0 [RATIO_PST1Q], LNxSSCR0 [AMP_RED_0], LNxSSCR0 [RATIO_PST1Q _0], and use eye diagram signal oscilloscope to measure, but the eye diagram is no changed.  In RM file, AMP_RED RATIO_PST1Q, the last line: Note: this field is read-only when this lane is operating as PCIe. So, how to modify the eye parameters for pcie interface?

 

Best Regards

Qiuju.ye

 

 

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ufedor
NXP Employee
NXP Employee

What exactly is not good with the PCIe signal?

Have you performed the PCIe signal integrity simulation using the processor's IBIS-AMI model?

 

Some background:

Most of the SerDes registers might be configurable for non-PCIe protocols. There is a reason for that: many other protocols like 10Base-KR don’t define a link training protocol in their industry spec. Therefore, the software is allowed to tweak and change to make it work. In other words, those protocols feature a “software-controllable” signal integrity tweak and link training standard.

            This is not the case for PCIe, which has a fully defined hardware-controlled signal integrity and link training protocol. Therefore, software is not allowed to modify it. Otherwise, the link partner would not understand the intention.

 

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