Configure EVT0_B, EVT1_B, EVT2_B, EVT3_B and EVT4_B as input pin on LS1043

[bhargavjayswal]

Currently I have utilize all interface and pin available on LS1043 and I require to have an extra GPIO to identify my board version. By reviewing schematic of LS1043ARDB , I find that EVT0 to EVT4 pins are pull up with 4.7K register and not used at anywhere.

In technical reference manual of LS1043, Appendix C represent EPU register descriptions. Where EPU base address is 2000_0000h. 

EVT0_ADDR -> 2000_0000 + (50h + (0 x 4h)) = 2000_0050     (EPEVTCR0)

EVT1_ADDR -> 2000_0000 + (50h + (1 x 4h)) = 2000_0054     (EPEVTCR1)

EVT2_ADDR -> 2000_0000 + (50h + (2 x 4h)) = 2000_0058     (EPEVTCR2)

EVT3_ADDR -> 2000_0000 + (50h + (3 x 4h)) = 2000_005C    (EPEVTCR3)

EVT4_ADDR -> 2000_0000 + (50h + (4 x 4h)) = 2000_0060     (EPEVTCR4)

So if I configure 0th bit DIR as 0b then it will configure as input pin then I can read status of that pin from EPRSRSVn.

As per my understating if ENTn_B pin is configure with external pull-up then I will get value 1 from EPRSRSVn register.if ENTn_B pin configure with external pull-down then i will get value 0 from EPRSRSVn register.

Request you to confirm this, please let me know for any improvement or changes.

Regards,

Bhargav Jayswal

[bhargavjayswal]

Thank you @SebastianG ,

I have posted one more query today but it is not reflecting in NXP community. Title for the query is "LS1043A : EMMC GPT partitioning and boot process". Could you please help for this as well.

[SebastianG]

Hi @bhargavjayswal, 

Yes, I will support in this query

[SebastianG]

Hi @bhargavjayswal,

This configuration seems good 

[bhargavjayswal]

Thanks for  update.

Now based  on above configuration, can we use this pin as an input gpio during u-boot to validate state of the pin whether is high or low? 

Regards,

Bhargav Jayswal

[SebastianG · Accepted solution]

Hi @bhargavjayswal,

Apologies for the delayed response,

Yes, you can use this pin as an input in order to validate the pin state