Hello everyone.
My goal is to get my LS1043a board to boot by SD and starting the system by shutting down cores 1, 2 and 3.
Once the system is up and running, i would like to see from uboot that such cores are disabled.
To do this I have create a custom boot via flexbuilder.
I made the boot from SD through this procedure PROCEDURE TO BOOT FROM SD
The problem is when I turn on u-boot it shows me this error:
What's the problem?
I don't understand where the problem is since in the previous attempts u-boot started me without problems, nothing has changed from the previous procedures where the card started with u-boot.
Solved! Go to Solution.
BL2 initializes the DRAM, then loads BL31, BL32, and BL33 images to the DDR memory after validating these images BL31, BL32, and BL33.
According to your error log, it seems that DDR controller initialization section provided in ATF is not suitable for your custom board.
In ATF source code flexbuild_lsdk2108/components/firmware/atf, please modify plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c according to your custom board.
You could modify ddr_raw_timing according to your DDR data sheet, then build atf image and deploy it to our custom board. Then use QCVS DDR tool to connect to your custom board to read from target board to create a QCVS DDR project, then use QCVS DDRv tool to connect to your target board to do validation and optimization to get the optimized DDR controller configuration parameters.
1. You could define CONFIG_STATIC_DDR in plat/nxp/soc-ls1043a/ls1043ardb/platform_def.h, and use static DDR configuration parameter.
2. You also could use DDR raw timing and modify rc timing and board timing in plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c calculated by DDRv tool.
BL2 initializes the DRAM, then loads BL31, BL32, and BL33 images to the DDR memory after validating these images BL31, BL32, and BL33.
According to your error log, it seems that DDR controller initialization section provided in ATF is not suitable for your custom board.
In ATF source code flexbuild_lsdk2108/components/firmware/atf, please modify plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c according to your custom board.
You could modify ddr_raw_timing according to your DDR data sheet, then build atf image and deploy it to our custom board. Then use QCVS DDR tool to connect to your custom board to read from target board to create a QCVS DDR project, then use QCVS DDRv tool to connect to your target board to do validation and optimization to get the optimized DDR controller configuration parameters.
1. You could define CONFIG_STATIC_DDR in plat/nxp/soc-ls1043a/ls1043ardb/platform_def.h, and use static DDR configuration parameter.
2. You also could use DDR raw timing and modify rc timing and board timing in plat/nxp/soc-ls1043a/ls1043ardb/ddr_init.c calculated by DDRv tool.