Content originally posted in LPCWare by OldManVimes on Mon Jul 21 00:48:13 MST 2014
Hi,
I've noticed that my version of the CMSIS source code for the Cortex-M0 does not include a function that exposes the ROR (a.k.a. RORS?) assembly instruction as a GCC function. It does exist in the CMSIS source code, but is only enabled for the Cortex-M3 (i.e. the __ROR function) via an #ifdef. According to the ARM documentation, the M0 supports a RORS instruction that appears to be comparable, so my question is why it is not exposed in the CMSIS for an M0?
Note that I'm not 100% sure my CMSIS version is the latest version. It was provided by the project creation wizard for a M0 project from LPCXpresso v6.x and might in theory have been updated since.
Anyway, I'm just curious about why it isn't supported since there are practical applications for using the register bit rotation functionality (as opposed to a shift).
Thanks,