Content originally posted in LPCWare by Albert on Tue Feb 01 09:52:49 MST 2011
No I can't see a valid clock signal at 1.27 pin, just until 300KHz.
Thanks for the steps, I had already used many times this method to debbug again.:D
I follow the advice on manual see:
The following sequence must be followed step by step in order to have PLL0 initialized
and running:
[COLOR=Red]1. Disconnect PLL0 with one feed sequence if PLL0 is already connected.
2. Disable PLL0 with one feed sequence.[/COLOR]
3. Change the CPU Clock Divider setting to speed up operation without PLL0, if desired.
4. Write to the Clock Source Selection Control register to change the clock source if
needed.
5. Write to the PLL0CFG and make it effective with one feed sequence. The PLL0CFG
can only be updated when PLL0 is disabled.
6. Enable PLL0 with one feed sequence.
7. Change the CPU Clock Divider setting for the operation with PLL0. It is critical to do
this before connecting PLL0.
8. Wait for PLL0 to achieve lock by monitoring the PLOCK0 bit in the PLL0STAT register,
or using the PLOCK0 interrupt, or wait for a fixed time when the input clock to PLL0 is
slow (i.e. 32 kHz). The value of PLOCK0 may not be stable when the PLL reference
frequency (FREF, the frequency of REFCLK, which is equal to the PLL input
frequency divided by the pre-divider value) is less than 100 kHz or greater than
20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time
has passed. This time is 500 μs when FREF is greater than 400 kHz and 200 / FREF
seconds when FREF is less than 400 kHz.
9. Connect PLL0 with one feed sequence.
I don't understend why my code doesn't work, I do something different on the manual?