Content originally posted in LPCWare by ktownsend on Fri Jan 22 00:18:56 MST 2010
Not to nag, but I think that there's perhaps a problem with the 16-bit timer example as well? You give you the following definition and commentary in timer16.h (though I don't remember if this is in the Keil or the LPCXpress examples ... there are some differences between them):
#define TIME_INTERVAL ((SystemFrequency/LPC_SYSCON->SYSAHBCLKDIV)/100 - 1)
/* depending on the SystemFrequency and AHB clock divider setting,
if SystemFrequency = 60Mhz, SYSAHBCLKDIV = 4, SystemAHBFrequency = 1/4 SystemFrequency,
10mSec = 150.000-1 counts */
The calculations are all fine, but won't providing 150,000 to MR exceed the 16-bit maximum value?
[B]UPDATE[/B]: Sorry ... the misunderstanding seems to be my own. The match register seems to accept a 32-bit value, since when I compared the two 16-bit timers side by side, one with 65,535 as an interval and the other with 150K they seem to behave as expected, though this isn't the behaviour I'd expect on first glance (the UM states "[FONT=Arial][SIZE=2][FONT=Arial][SIZE=2]Four 16-bit match registers that allow ...[/SIZE][/FONT][/SIZE][/FONT]" on p.224).