Clock configuration on the LPC13xx

[lpcware]

Content originally posted in LPCWare by TomT617 on Tue Mar 02 10:47:11 MST 2010
Hello all,

I’m new to the arm processors. This week I’ve been playing with the LPCXpresso with the LP1343 on it. I want to configure the Clock Generation Unit to produce system clock of 72MHz. Can't seem to get it working. Does anyone know of any good examples of this. Been trying stuff like:

LPC_SYSCON->SYSOSCCTRL = 00;// 1-20MHz range + Oscillator not bypassed
LPC_SYSCON->PDAWAKECFG = 00;// enable system oscillator module
LPC_SYSCON->SYSPLLCLKSEL = 1;// PLL is input for the  System oscillator
LPC_SYSCON->SYSPLLCTRL = 105;// M
LPC_SYSCON->SYSPLLCLKUEN = 1;// start clock change


Thanks,
Tom.

[lpcware]

Content originally posted in LPCWare by Luis Digital on Fri Mar 19 11:45:06 MST 2010
I found the main problem: "Build" or "Build All" does not take into account the changes in files.

First I did a "Clean" and now the parameters have effect.

"LPC_SYSCON->SYSPLLCTRL=0x03" is 48 MHz (4*12)

I also changed the value of "PSEL" with different values, but the frequency did not change. I think I misunderstood the use of "PSEL".

[lpcware]

Content originally posted in LPCWare by Luis Digital on Thu Mar 18 17:56:41 MST 2010
Even more confused.

I used the function "CLKOUT_Setup (CLKOUTCLK_SRC_MAIN_CLK)" to see the clock changes, divided among 72, to obtain an output of 1 MHz, with a main clock of 72 MHz (default in "system_LPC13xx.c").

The frequency counter showed a frequency of 1000119 Hz, something expected.

Then I changed the parameter "LPC_SYSCON->SYSPLLCTRL=0x05" with "LPC_SYSCON->SYSPLLCTRL=0x25" as you wrote here. And the output frequency was the same.

I changed the multiplication parameter to 3, and the measured frequency remained the same.

As if these parameters had no effect.

I'm changing the configuration of the constants in the file "system_LPC13xx.c", and compiling everything.

Some light, please.

Thank you.

[lpcware]

Content originally posted in LPCWare by Luis Digital on Wed Mar 17 15:47:30 MST 2010
I'm confused.

Pag. 14 User manual
6:5 PSEL
Post divider ratio P. The division ratio is 2 × P.

If P = 2 then P = 2 * P = 4

MainClock = 72 MHz / 4 = 18 MHz

---

In system_LPC13xx.c

P = 2 (PSEL =0)

MainClock = 72 MHz / 2 = 36 MHz

Is that the speed at which these microcontrollers are all running?

Thanks.

[lpcware]

Content originally posted in LPCWare by NXP_USA on Thu Mar 04 15:21:26 MST 2010

---

Quote: TomT617
Hello all,

I’m new to the arm processors. This week I’ve been playing with the LPCXpresso with the LP1343 on it. I want to configure the Clock Generation Unit to produce system clock of 72MHz. Can't seem to get it working. Does anyone know of any good examples of this. Been trying stuff like:

LPC_SYSCON->SYSOSCCTRL = 00;// 1-20MHz range + Oscillator not bypassed
LPC_SYSCON->PDAWAKECFG = 00;// enable system oscillator module
LPC_SYSCON->SYSPLLCLKSEL = 1;// PLL is input for the  System oscillator
LPC_SYSCON->SYSPLLCTRL = 105;// M
LPC_SYSCON->SYSPLLCLKUEN = 1;// start clock change


Thanks,
Tom.

---

Hi Tom,

In a CMSIS project, the CGU would be set up by default for 72 MHz. It would be initialized by the code in the SystemInit() function in the CMSIS library file system_LPC13xx.c which is called from the Code Red startup code in cr_startup_lpc13.c.

Looking at the init code that you posted, PDRUNCFG should be used to enable the System oscillator (external crystal) and PLL instead of PDAWAKECFG.

SYSPLLCTRL should be set to 001 00101 (binary) which is 25 hex or 37 decimal. This is  because the PLL needs an M value of 6 and a P value of 2 to generate 72 MHz. The layout of this register is described in section 5 of the User's Manual. To calculate M and P, see section 10 of the User's Manual for the PLL diagram. First, the 12 MHz input clock must be boosted to something between 156 MHz and less than 320 MHz. This is called the CCO clock. CCO = FCLKIN*M*P*2 = 288 MHz. Afterward, the CCO clock must be divided to generate FCLKOUT for the core. FCLK must be 72 MHz or less. FCLK = CCO/M. The process here should be to take the desired PLL output clock (FCLKOUT=72 MHz) and divide it by the input clock (FCLKIN=12 MHz) to get M (6). Now pick a P value that results in a CCO > 156 MHz remembering that CCO = FCLKOUT * P * 2.

Regarding SYSPLLCLKUEN, the PLL settings will not be updated until ENA is set to 0 and then set back to 1. In the posted code it is only set to 1.

Some more tasks that are needed (see the CGU diagram in Chapter 3):
* Select the PLL as the main clock with MAINCLKSEL
* Set the clock divider to /1 with AHBCLKDIV (this is a reset default)

Here is some sample code to set up the PLL for 72 MHz with a 12 MHz crystal. I have commented out things that are already set by default out of reset.

//LPC_SYSCON->SYSOSCCTRL  = 0;   // 1-20MHz range + Oscillator not bypassed
LPC_SYSCON->PDRUNCFG   &=
         ~(1<<5);               // power up system oscillator
LPC_SYSCON->SYSPLLCLKSEL = 1;// System oscillator is input for the PLL
LPC_SYSCON->SYSPLLCLKUEN = 0;// clear SYSPLLCLKUEN
LPC_SYSCON->SYSPLLCLKUEN = 1;// start pll input clock change
LPC_SYSCON->SYSPLLCTRL = 0x25;// PLL P=2, M=6 for CLKIN x 6 = 72 MHz
LPC_SYSCON->PDRUNCFG   &=
         ~(1<<7);               // power up system pll
while(!(LPC_SYSCON->SYSPLLSTAT & 0x01)); // Wait for PLL to lock
LPC_SYSCON->MAINCLKSEL   = 3;   // main clock = system pll clock out
LPC_SYSCON->MAINCLKUEN = 0;// clear MAINCLKUEN
LPC_SYSCON->MAINCLKUEN = 1;// start main clock change to pll output

//LPC_SYSCON->SYSAHBCLKDIV = 1;   // core/peripheral clock = main clock divided by 1
                                // note some peripherals don't go through this divider
                                // see CGU divider