The Cortex-M0 and Cortex-M0+ CPU cores can be implemented with one of two hardware multiply options:
Fast : This allows the MULS instruction to execute in a single cycle
Small : An iterative multiplier that takes 32 cycles to execute a MULS instruction.
For most NXP MCU's which use these cores, the 'Fast' option is implemented. However the Cortex-M0 on LPC43xx and the Cortex-M0+ on LPC5410x implement the 'Small' option.
Changing compiler behavior for 'Slow' multiplier implementation
To multiply two integer variables the GCC compiler used by LPCXpresso IDE will always use a MULS instruction.
But for a multiply by a constant, the compiler can either use a sequence of add / subtract / shift operations, or the MULS instruction.
By default, the compiler assumes that a 'Fast' multiplier option is implemented by the target hardware, thus it will use a MULS instruction as this is assumed to be fastest and smallest. However this is not actually the case for Cortex-M0 on LPC43xx and the Cortex-M0+ on LPC5410x, and in some cases it may be preferable to generate sequence of add / subtract / shift operations in order to obtain better performance.
In order to allow this, LPCXpresso 7.6 introduced a new mechanism to allow the user to instruct GCC to generate add / subtract / shift operations.