Verify the ADC speed with LPC5460

[georgechancello]

I am trying to verify the ADC speed with the LPCXpresso54608 eval board.

I stated with the lpc_adc_dma example and then modified the dma to have a linked list of 100 descriptors which then places the ADC data into an array of 100.  I set the ADC to be in burst mode .  I then send in a 100KHz sine wave, but what I receive looks like the ADC is sampling at maybe 400KHz, versus the 180 / 3 =  60MHz that I set it to.

Is there a better way to do this.

see attached file

Thanks

[georgechancello]

Thank you for that comment and I already looked at the page.

My DMA is setup sort of like a ping pong.  What I did was a link list of 100 descriptors, which will fill an array of 100 variables.  This allowed me to just get 100 samples and then stop the ADC, since I am just doing a proof of concept I thought this was the easiest way to verify the idea.  In the final design I will use a ping pong descriptor and continually read the ADC.

This DMA read is the same as what I had in the original post, and was the reason I asked for help.  Although at that time I was not sure the ADC was working properly.  After your other comments I was able to determine the ADC is in fact running at required speeds, but it seems the DMA is running at a much slower speed.

Can you tell if I am doing something incorrect in the DMA setup to justify the speed reduction?

[georgechancello]

Thank you for the help.

I did switch to interrupt based and was able to verify the ADC is sampling at ~60MHz.

But when I switch back to DMA control it does not sample as fast it is ~30 times slower.  When I input a 100KHz signal I get ~30 samples using IRQ, but only get 3 when using DMA.

What could be going on here?

[jeremyzhou]

Hi George Chancellor,

I think this application may help you.

DMA Ping-Pong application 

Have a great day,
TIC

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[georgechancello]

Thank you for the reply.

I was aware of the 15 clock cycles, which would should make the ADC sample rate 4MHz not 400KHz.

The 400KHz implies the ADC is running at 6MHz.

Based on the end code that I am trying to run, if I can get >5MHz sample rate my design will work fine.

[jeremyzhou]

Hi George Chancellor,

Thanks for your reply.

Yes, I made a miscalculation.

To confirm the ADC conversation speed, you can use the Systick timer to count or toggle the output pin in the ADC interrupt function, then you can evaluate the the ADC conversation speed by observing the output pin in oscilloscope.

Hope it helps.
Have a great day,
TIC

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[jeremyzhou]

Hi George Chancellor,

Thank you for your interest in NXP Semiconductor products and 

for the opportunity to serve you.

After review your code, I get that ADC resolution is 12 bit, and sample time configuration is 0x0, which means complete a conversation will need 15 ADC clocks, then sampling frequency can be calculated via following formula.

F= 60 MHz/15= 4000 KHz.

Have a great day,
TIC

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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