Hi Carlos,
I am using LPC54605J512.
The problem I am facing is that I want to use I2S DMA in a mono mode, so I don't have to duplicate data because I am short of RAM memory.
I have configure the DMA and I2S as follows, using the Linked transfers (linked list) mode. However the last block of the buffer always produces a glitch, I am not sure what is going on...
/**
* Channel transfer configuration.
**/
#define I2S_XFERCFG_INVALID (0 \
| !DMA_XFERCFG_CFGVALID /* Not valid until s/w writes SETVALID reg */ \
| DMA_XFERCFG_RELOAD /* Follow next pointer to next descriptor */ \
| DMA_XFERCFG_SWTRIG /* Assert s/w triggering immediately */ \
| !DMA_XFERCFG_CLRTRIG /* Don't clear trigger at end of txfer */ \
| DMA_XFERCFG_SETINTA /* Set interrupt A on end of txfer */ \
| !DMA_XFERCFG_SETINTB /* Don't set interrupt B on end of txfer */ \
| DMA_XFERCFG_WIDTH_16 /* I2S FIFO requires 32-bit accesses */ \
| DMA_XFERCFG_SRCINC_1 /* Source (memory) increment of 1 access width */ \
| DMA_XFERCFG_DSTINC_0 /* Destination (FIFO) does not increment */ \
| DMA_XFERCFG_XFERCOUNT(I2S_BLOCK_SIZE)) /* Transfer size is fixed at block size */
static const I2S_AUDIO_FORMAT_T sAudioFmtTx =
{
I2S_TX, /*!< Data direction: tx or rx */
NORMAL_MASTER, /*!< Master / Slave configuration */
I2S_CLASSIC, /*!< I2S mode */
false, /*!< right channel data in low portion of FIFO */
false, /*!< left justify data in FIFO */
false, /*!< data source is the D-Mic subsystem */
false, /*!< SCK polarity */
false, /*!< WS polarity */
2, /*!< Flexcomm function clock divider; use MCLK/2 */
1, /*!< Channel Number - 1 is mono, 2 is stereo */
16, /*!< Word Width */
32, /*!< Frame Width */
0, /*!< Data position in the frame */
0, /*!< FIFO interrupt trigger depth: 0 trigger on empty */
};
Jacinto
