Content originally posted in LPCWare by PhilYoung on Wed May 16 15:51:26 MST 2012
This is an undocumented but known problem,
It's not a PLL problem, but due to the internal voltage regulator.
The trick is to switch the CPU clock first to an intermediate frequency then wait for the PSU to stabilize before switching to a higher frequency.
Since I use PLL0Audio to clock the CPU I set up PLL1 to 150 MHz and PLLAudio to 200 MHz, first I use PLL0Audio / 2 using iDIVA on PLL0Audio, this gets to 100 MHz, then switch to PLL1, then to PLL0Audio, leaving a few ms between each switch.
You can in theory just go to 100 then 200MHz, but this seemed less reliable.
the code is as follows ( excluding the PLL setup code )
#define CPU_CLK_SRC 8
SetClkSource(&LPC_CGU->BASE_M4_CLK,0xC);// = (1 << 11) | (8 << 24); // DIVA ( 100.8 MHz)
Pause(1000);
SetClkSource(&LPC_CGU->BASE_M4_CLK,0x9);// PLL1 ( 150 MHz)
Pause(1000);
SetClkSource(&LPC_CGU->BASE_M4_CLK,CPU_CLK_SRC);// = (1 << 11) | (8 << 24); // PLL0_AUDIO
regards
Phil.