Undocumented SPIFI Interrupt Handler

[lpcware]

Content originally posted in LPCWare by avenuti on Wed Jan 06 14:28:21 MST 2016
UM10430 LPC18xx ARM Cortex-M3 microcontroller
Rev 2.8 - 10 December 2015

This user manual is missing information on the SPIFI Interrupt Handler.

In table 72, Chapter 8 (NVIC), Interrupt ID 30 is listed as "Reserved", but enabling this bit in NVIC->ISER[0] enables the SPIFI interrupt.
(The corresponding table in the manual for LPC43xx lists this as the SPIFI interrupt)

Furthermore, cmsis_18xx.h in lpc_chip_18xx in LPC OPEN lists this RESERVED4_IRQn, but calling NVIC_EnableIRQ(RESERVED4_IRQn); also correctly enables the SPIFI interrupt.

cr_startup_lpc18xx.c does declare SPIFI_IRQHandler(), which leads me to believe this interrupt is meant to be supported.


Is this simply a mistake in the manual, or is this feature unsupported?
If it is unsupported, why does the manual list INTEN in table 336 and and INTRQ in table 343, both in Chapter 21 (SPIFI)?

[lpcware]

Content originally posted in LPCWare by avenuti on Thu Jan 21 09:58:48 MST 2016
Yappi, MikeSimmonds;

I am currently utilizing this interrupt on an 1837 to handle DMA transfers. I have posted details here: https://www.lpcware.com/content/forum/dma-tofrom-spifi#comment-1149080

The SPIFI interrupt is triggered when the SPIFI finishes sending a command. For example, if you send a page program command where the data is 512 bytes long, the SPIFI is busy for approximately 110 microseconds (core at 180 MHz, SPIFI clock at 90 MHz) while those bytes are sent to the flash. After this time the SPIFI interrupt is triggered (for my flash chip, the chip itself is busy for another ~380 microseconds while the page is programmed). Note that the interrupt bit 22 (INTEN) of the SPIFI CTRL register must also be set. Your interrupt function should be named 'SPIFI_IRQHandler'. Bit 5 of the SPIFI STAT register (INTRQ) is used to clear the pending interrupt status (note also that there is a typo in the manual for INTRQ, stating that a single bit resets to 5).

I've done a lot of work with SPIFI over the past couple months. Feel free to ask any other questions and I'll do my best to respond.

[lpcware]

Content originally posted in LPCWare by mc on Wed Jan 20 07:40:13 MST 2016
Hi All,
SPIFI interrupt is implemented on this chip. We will  document it in UM soon.

[lpcware]

Content originally posted in LPCWare by Yappi on Tue Jan 19 08:54:59 MST 2016
Hi,
I'm also interested in using this feature, if it is supported and will be available on 18xx variants going forward.  NXP, can you look into this?  Is this just a case where the documentation needs to be updated?
Thanks!

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Sat Jan 09 22:16:57 MST 2016

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Quote: avenuti
UM10430 LPC18xx ARM Cortex-M3 microcontroller
Rev 2.8 - 10 December 2015

This user manual is missing information on the SPIFI Interrupt Handler.

In table 72, Chapter 8 (NVIC), Interrupt ID 30 is listed as "Reserved", but enabling this bit in NVIC->ISER[0] enables the SPIFI interrupt.
(The corresponding table in the manual for LPC43xx lists this as the SPIFI interrupt)

Furthermore, cmsis_18xx.h in lpc_chip_18xx in LPC OPEN lists this RESERVED4_IRQn, but calling NVIC_EnableIRQ(RESERVED4_IRQn); also correctly enables the SPIFI interrupt.

cr_startup_lpc18xx.c does declare SPIFI_IRQHandler(), which leads me to believe this interrupt is meant to be supported.


Is this simply a mistake in the manual, or is this feature unsupported?
If it is unsupported, why does the manual list INTEN in table 336 and and INTRQ in table 343, both in Chapter 21 (SPIFI)?

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NXP: Any comments?

Mike.