UART Status Register Bits for LPC54102

[robertalkire]

I am currently working on UART0 receive via interrupt with FreeRTOS. It was detecting error bits when it should not have.  I am using LPCopen 3.03 with GCC 4.9.3 on a LPC54102 (custom board) M4F only.

The problem was traced to a discrepancy between the data sheet and the include file uart_5410x.h with the UART Status Register Bits. It defines UART_RXDERR as 0xF100. These bits map to (8) OVERRUNINT, (12) START, (13) FRAMERRINT, (14) PARITYERRINT, and (15) RXNOISEINT. 

START is not an error, it is status of when a start bit is seen on the receiver input. The use of the start status would not be handled by an error routine. Also there is a define for UART_START.

It would also be more useful to have individual defines for each of the status as was done in the interrupt register bits and on other processors.  

Another  error  exists in the same UART Status Register bits, UART_TXDERR maps to bit 9 (0x200). Bit 9 is shown as reserved in the data sheet although the comment shows TX underrun. The data sheet mentions underrun in the feature list for the UART but there aren't any bits in the interrupt register, status register for underrun. 

[jeremyzhou]

Hi Robert Alkire,

Thank you for your interest in NXP Semiconductor products and 

for the opportunity to serve you.

First, thanks for your reporting.

I was wondering if you can exemplify the detailed steps of testing such as how many break point needs and which line the break points locate.

After confirming, I'll escalate the question to AE team for the deeper investigation.

I'm looking forward to your reply.

Have a great day,
TIC

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[robertalkire]

Just to clarify, it did not take breakpoints to solve this. The behavior did not match the datasheet and I found the LPCopen include files to be in error. As I've discovered other errors in LPCOpen for this processor, I check against the datasheet before getting into debugging. For example, the datasheet UM10850 Rev 2.4 pg 256 states: 

Interrupts available for Receiver Ready, Transmitter Ready, Transmitter Idle, change
in receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS
detect, and receiver sample noise detected

I could not find any bits related to Underrun in STAT, INTENSET, INTENCLR, or INTENSTAT.  If they don't exist, why does UART_TXDERR have a bit for the UART status register LPCOpen 3.03 LPCOPen5410x/lpc_chip_5410x/inc/uart_5410x.h line 52 assigned bit 9 that the datasheet states is reserved.

Also why is, in the same file, bit 12 START part of UART_RXDERR. Data sheet states:

This bit is set when a start is detected on the receiver input. Its purpose is
primarily to allow wake-up from Deep-sleep or Power-down mode immediately
when a start is detected. Cleared by software.

So I just noticed something when reviewing this. The UART status, interrupt, and configuration  register definitions are defined twice in the uart_5410x.h. First from lines 46 to 83, and second from 114 to 171. The example in periph_uart_rb project uses the second set and it is a far better definition and more accurate representation of the registers. I had initially missed this when my search found the first UART Status. It looks like that this is a remnant of old code that should have been deleted and wasn't.