Content originally posted in LPCWare by avenuti on Mon Nov 23 11:18:03 MST 2015
Okay, I think I'm finally making progress here.
Went back to the function spifiInit, which initially had been causing me problems. If I called that function with the reset flag set 'true', the library would not initialize correctly, causing spifiGetHandleMemSize to return 0 and spifiInitDevice to return NULL. Calling spifiInit with the reset flag set 'false' would fix this, and according to the documentation "in most cases, a reset isn't needed".
Curiously, spifiInit does nothing whatsoever if that reset flag is set 'false', so I figured I'd go through it line-by-line and figure out what inside spifiInit was causing problems.
It turns out that line 344 (of spifi_dev_common.c) was the culprit, setting the feedback clock to 1, or SPIFI_CTRL_FBCLK(0).
Not only did setting this to 0 allow me to run spifiInit with reset 'true', but doing so fixed my quad mode / high speed reading problem! I can now run at 180 MHz, with the SPIFI clock at 60 MHz, and both reads and writes are functioning properly.
It turns out that not setting SPIFI_CTRL_RFCLK(1) (by skipping the spifiInit reset completely) was the actual cause of my read problem. Setting SPIFI_CTRL_RFCLK(0) (with the feedback clock also 0) reintroduced my problem.
Can you please give me some insight as to what exactly is going on with RFCLK/FBCLK enabled or disabled? The documentation for these is clear but not meaningful.