SCT (lpc43xx): Additional interrupt requests for each event....

[lpcware]

Content originally posted in LPCWare by lpc_guy469 on Thu Mar 13 08:38:29 MST 2014
Hello....


I am having some difficulty with the LPC43xx SCT IRQ handler. 

The SCT Flag Enable register (address=0x400000F4) contents are being programmed with 0x00000004 (Event 2).   So it is expected that an SCT interrupt request should only occur when Event 2 occurs.  However, the SCT is interrupting the LPC43xx with 2 requests for every one of Event 2.

Also, the interrupt latency is 108ns.  This figure is approximately 19 clock cycles.  Is this behavior considered normal or is there a way to shorten this latency.

Thank you in advance for your assistance.


.....lpc_guy469

[lpcware]

Content originally posted in LPCWare by roboknight on Thu Nov 20 12:13:54 MST 2014
I am tacking on to this post because I'm also having issues with the SCT interrupts, however my issues are related to CTIN_x inputs.  I am attempting to catch a 1-wire-type signal with the SCT.  So far, I've been able to CREATE a signal with the SCT just fine (coding by hand).  I've looked at the RC5 SCT example code for both send and receive.  My issue seems to be that no matter WHAT I try, I cannot seem to get the lpc4330 to generate any interrupts for any edges on my CTIN_x input.  The specifics are as follows:

1) LPC4330-Xplorer board from NGX.  This board contains 2 headers.
2) Using GPIO0[8] configured for CTOUT_7 I have 8 states, 2 clears CTOUT_7, and 0, 4, and 6 SET CTOUT_7
    States 3, 7, and 8 generate interrupts to help generate output.

3) Usng GPIO1[9] configured for CTIN_5, I have connected the GIMA CTIN_5 to CTIN_5 (which should be the default anyway), I have states 9-12.  State 9 does a capture from the high part of the timer on a falling edge for CTIN_5 Only.  State 10 does a capture from the high part of the timer on a rising edge for CTIN_5 only.  Only state 10 is supposed to generate an interrupt.  State 11 was a timeout state that WAS generating an interrupt, but it was much too high a frequency so it locked up the chip, so I cut it out for now.  It is supposed to be a timeout.  State 12 is a dummy state to help bookkeeping.

The interrupts for 0, 4, and 6 are working.  No matter WHAT I've tried, I can not seem to generate any interrupts for anything on ANY kind of input to GPIO1[9] (which I've configured as Function CTIN_5 (1), and as straight GPIO, which I didn't expect to work.)

So, my question is:  What steps should I take to make sure a signal can generate an interrupt on the selected SCTIN_x?
I would post code, but the code is part of something else that is quite extensive and currently I don't have a scaled down example that show the work.  But basically, the flow for SCT configuration is thus:

1) Enable SCT clock
2) Reset SCT (didn't really seem necessary, but I threw it in)
3) Set GIMA SCTIN_5 to CTIN_5 (didn't seem necessary as this is the default).
4) Set CREG6 CTOUTCTRL to 1 (This should only apply to CTOUT, not CTIN, but I'm in kitchen sink mode here).
5) SCT->Config = 0 (split timer)
6) Set up my 6 low match/matchreload registers
7) Set up my first 9 events (0-8)
8) Set up the output so event 2 clears, events 0,4, and 6 set CTOUT_7
9) All states 0-8 should limit low timer half.
10) set match/reload 7,10 for using in "upper" events (input events)
11) Set match/reload 8/9 for capture instead of match/reload
12) Set capture control so that capture 8 works on event 9 and 9 works on event 10.
13) Set events 9 & 10 for I/O.  They occur in all states, HEVENT set to 1, OUTSEL = 0, IOSEL = 5, IOCOND = 2,1 (2 for 9, 1 for 10... falling, rising) , COMBMODE = 2, stateV is added, stateV = 0.
14) configure pins for CTIN_5 no pullup/down and as GPIO input (which is default anyway).
15) configure pins for CTOUT_7 pullup/pulldown and as GPIO output
16) stop both counters
17) Attach to IRQ SCT
18) Reset states, reset count, set initial CTOUT_7 to high.
19) Enable SCT IRQ,
20) Setup Even interrupt as (1 << 3) | (1<<7) | (1 << 8) | (1<<10)
21) Clear EVFLAG
22) Start high timer

So, events 3, 7 and 8 seem to be occurring and generating interrupts.  The problem is event 10.  Is there something else I'm supposed to do?  Again, I've looked at RC5_receive for clues, to no avail.

NOTE: Low timer gets enabled later when I want to generate some output.

Thanks in advance for any help.

[dimitrissideris]

  I've looked at the RC5 SCT example code for both send and receive.

Can you please share the code that you are referring?

[lpcware]

Content originally posted in LPCWare by TheFallGuy on Thu Mar 13 12:14:27 MST 2014

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Quote: JoeHale
Hi,

With respect to the latency I think that the Cortex M4 should have a 12 cycle interrupt latency.

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12 cycles assumes a 'perfect' memory system (no wait states). If you are running from flash (especially external flash), then you will have wait states, which will certainly increase latency.

[lpcware]

Content originally posted in LPCWare by JoeHale on Thu Mar 13 11:34:00 MST 2014
Hi,

You should not get the interrupt called twice for each event. Could you provide a snippet of your code please so that I can investigate further. Also, are you using the Red State tool to generate the code or are you generating it by hand?

As an aside: the SCT Flag Enable register is at 0x4000 00F0. The register at 0x4000 00F4 is the SCT event flag register ( for clearing the interrupt).

With respect to the latency I think that the Cortex M4 should have a 12 cycle interrupt latency.

Regards,