Problem in setting Spifi Clock frequency to 90Mhz

[lpcware]

Content originally posted in LPCWare by praveen.9123 on Tue Apr 29 23:59:57 MST 2014
Hi,
   I am using lpcopenv2.02 source code for the platform of lpc4330 xplorer board.
The following code running the core clock frequency at 204MHz and Spifi Peripheral and base clock running at 68MHz.


/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
   Divide rate is based on CPU speed and speed of SPI FLASH part. */
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 3);
Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);

When i set the clock for SPIFI 90Mhz the core is hanging somewhere it is not responding and the core is running at 204MHz.
/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
   Divide rate is based on CPU speed and speed of SPI FLASH part. */
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 2);
Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);

[lpcware]

Content originally posted in LPCWare by metraTec on Mon Feb 29 02:28:18 MST 2016
Just for information: The same is with the LPC Link 2 board (LPC 4370). 96 MHz does cause a crash, 84 is working. Perhaps the same flash.

I'm a bit confused it worked when loading and running the code with debugger.

Anyways: Problem fixed just the same way (Divider by 3)

[lpcware]

Content originally posted in LPCWare by bavarian on Mon May 05 04:12:11 MST 2014
Hello Praveen,

the basis for the SPIFI clock is always the system frequency. If the system frequency is higher than the maximum qSPI frequency then you need to insert an integer divider.
This results e.g. in following clock settings:

[list]
  [*] Core @ 204 MHz  -->  SPIFI @ 204/3 MHz = 68 MHz
  [*] Core @ 240 MHz  -->  SPIFI @ 240/3 MHz = 80 MHz
  [*] Core @ 160 MHz  -->  SPIFI @ 160/2 MHz = 80 MHz
[/list]

If you don't care about power consumption, try to use 240MHz. It is clearyl out of spec, but should work in case you switch the PLL on in steps to give the internal regulators a chance to adapt to the higher current.

Regards,
NXP Support Team.

[lpcware]

Content originally posted in LPCWare by praveen.9123 on Sun May 04 20:09:10 MST 2014
Hi,
    Thanks for the support. I am not using out-off QSpifi flash.  Is there any possibility to keep the clock exactly 80Mhz for SPIFI clock frequency. Can u resolve these problem.

[lpcware]

Content originally posted in LPCWare by mc on Sat May 03 15:01:18 MST 2014
Hi Preveen,
LPC4330 Xplorer board contains Spainsion S25FL032P QSPI flash device. This device can't work beyond 80MHz. So please change clock to only upto 80MHz. As drs mentioned in his post, it is safe to put routines which modify clock in the RAM. In this way you are not depending on QSPI flash behaviour with the clock change.

Hope this help.

[lpcware]

Content originally posted in LPCWare by drs on Fri May 02 17:04:05 MST 2014
Are you running this code out of SPIFI? We do not recommend this. If you are you might want to try changing the SPIFI base clock from RAM to see if this affects your situation.

[lpcware]

Content originally posted in LPCWare by praveen.9123 on Wed Apr 30 00:02:53 MST 2014
Please help me how to resolve this.

Regards,
Praveen.