Porblem with setting up LCD Clk for lpc1857 running 180MHz

[lpcware]

Content originally posted in LPCWare by salimnawaz on Fri Oct 11 04:41:08 MST 2013
hi!
i am working on a lpc1857 development kit that comes with a colour lcd

the demo code uses nxp driver lib
i have set lpc1857 to 180mhz n it runs without any issue. the following is used for this purpose

uint32_tCGU_Init(void){
CGU_SetXTALOSC(12000000);
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
// Disable PLL1 CPU hang???
//CGU_EnableEntity(CGU_CLKSRC_PLL1, DISABLE);

//PLL1 Setup
// CGU_SetPLL1(6);// original
// modified by salim on 2 Oct 2013 for 2 step increase in frequency
// as mentioned in User Manual Section 10.2.1 page 89
// from 12MHz to 72MHz(<90MHz), 72 Mhz to 108MHz and 108MHz to 180Mhz
//CGU_SetPLL1(MUL_1);
CGU_SetPLL1(MUL_6);// Set Pll1 to 72 MHzLow Frequency
CGU_SetPLL1(MUL_9); // Set Pll1 to 108 MHz Mid Frequency
CGU_SetPLL1(MUL_15);// Set Pll1 to 180 MHz High Frequency

// end salim

CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3);
CGU_UpdateClock();
return 0;
}


for setting up LCD Clock  i use following code:

        CGU_SetDIV(CGU_CLKSRC_IDIVE, LCD_CLKDIV); // LCD_CLKDIV was 15 when LPC was running at 72Mhz
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_CLKSRC_IDIVE);
CGU_EntityConnect(CGU_CLKSRC_IDIVE,CGU_BASE_LCD);

I have tried varying LCD_CLKDIV but when i set LPC at frequencies greater than 120 MHz my Lcd displays gets distorted really bad. when running at 120 MHz and below changing LCD_CLKDIV changes refresh rate of the lcd but its works fine. i suppose that code is fine... so m unable to understand what exactly is going wrong.

so can anyone guide through this issue????

thanks and regards
Salimnawaz

[lpcware]

Content originally posted in LPCWare by bavarian on Wed Jan 13 07:36:33 MST 2016
The LPCOpen examples rely on the existence of the chip library and the board library. These are created in separate builds.
So please build them before, then the compiler run for the example will also be fine.

Regards,
NXP Support Team.

[lpcware]

Content originally posted in LPCWare by tom739 on Tue Dec 29 20:39:09 MST 2015
Hi,

Compiled with the IAR 6.50.6, there is an error of "could not open board_keil_mcb_1857.a". Where to find or download the board_xx_xx_xx.a file? Thanks.

[lpcware]

Content originally posted in LPCWare by tom739 on Tue Dec 29 20:39:05 MST 2015
Hi,

Compiled with the IAR 6.50.6, there is an error of "could not open board_keil_mcb_1857.a". Where to find or download the board_xx_xx_xx.a file? Thanks.

[lpcware]

Content originally posted in LPCWare by salimnawaz on Fri Oct 18 07:41:46 MST 2013
thanks a ton bavarian....
U pointed out d correct mistake i was doing.
I did those necessary changes sdram initialization and now the display works like a charm...
Thanks a ton again

best regards,
salim

[lpcware]

Content originally posted in LPCWare by bavarian on Thu Oct 17 00:42:43 MST 2013
Hello,

I can't find an example in this driver lib which fits to the display on the KEIL board, so I assume that you have written your own example.
My best guess is that you have problems on the display buffer side, The display buffer is in SDRAM, if you operate above 120MHz you need to change the frequency for the SDRAM memory interface to CPU_CLK / 2.
If you don't do that you will see a lot of read/write erors on the SDRAM bus --> pixel errors on the display.

There is nothing against changing the clock divider for the LCD on the fly, so your code is correct here

An example of a display running in a 180MHz core clock and 90MHz SDRAM bus configuration can be found in the folder

   . \Keil\ARM\Boards\Keil\MCB1800\Demo

but using another driver structure from KEIL.But in the setup of the memory interface you will see what you need to do to divide the core clock by 2 for the memory interface.

There are also LCD examples for the MCB1857 board in the LPOpen package, using our new driver structure:

http://www.lpcware.com/system/files/lpcopen_v1.03.zip

Regards,
NXP Support.

[lpcware]

Content originally posted in LPCWare by salimnawaz on Mon Oct 14 01:05:00 MST 2013
Hi i have managed to solve this issue partially
the problem was with CGU file

i had to replace this bug in NXP lib

#define CGU_REG_BRANCH_STATUS(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset+4))
#define CGU_PER_BRANCH_STATUS(x) (*(uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset+4))

with this one
#define CGU_REG_BRANCH_STATUS(x) (*(volatile uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].RegBranchOffset+4))
#define CGU_PER_BRANCH_STATUS(x) (*(volatile uint32_t*)(CGU_CGU_ADDR+CGU_PERIPHERAL_Info[x].PerBranchOffset+4))

now i able to run the processor at 168Mhz and the display works fine but when i further increase it to 180 MHz display again gets distorted... still no luck with clock divider....