LPC824 SCTimer cannot unset the CTRL::STOP bit flag

[fjrg76]

Hi,

Right after clearing the CTRL::HOLD bit flag (in order to start the timer), the CTRL::STOP bit flag is automatically set, and there's no way to clear it!

This same application runs nicely on a LPC812MAX board:

A synchrony signal is shown on yellow color, while an output signal is shown in blue color. What I'm trying to achieve is (which I've already done it in the LPC812 uC):

The problem with the LPC812 is that you forgot to include an ADC, so for my application I needed to find a similar device.

Now, what's the problem with the LPC824? Let me show you the last instruction after the timer has been configured:

//Chip_SCT_ClearControl( LPC_SCT, SCT_CTRL_HALT_L ); // both instructions are the same
LPC_SCT->CTRL_U &= ~( 4 );

After executing this instruction the CTRL::STOP bit flag is set:

And none of these instructions are capable of clearing the STOP flag:

Chip_SCT_ClearControl( LPC_SCT, SCT_CTRL_STOP_L );
LPC_SCT->CTRL_U &= ~(0x2);

At the end of this post I'll show you the complete code for such configuration; but before in doing so, I found that if I comment this next instruction out, which stops the timer in EVENT1, then the STOP flag is not set; however, my application is still failing at its purpose:

LPC_SCT->STOP_U = SCT_EVT_1;

Thank you in advance. Any hint or suggestion is appreciated.

Here is my code (SystemCoreClock is running at 30MHz):

void sct_fsm_init (void)
{
Chip_SCT_Init(LPC_SCT);

Chip_SCT_Config(LPC_SCT,
   SCT_CONFIG_32BIT_COUNTER   // 32 bits
 | SCT_CONFIG_AUTOLIMIT_L )   // timer resets itself
 ; 

// F=120Hz, steps=1000:
Chip_SCT_SetControl( LPC_SCT,
   SCT_CTRL_HALT_L
 | SCT_CTRL_CLRCTR_L
 | SCT_CTRL_PRE_L( SystemCoreClock/120000 - 1 ) )
 ;

LPC_SCT->STATE_U = 0;
// no states (UM_LPC812: 10.7.12; UM_LPC824: 16.7.12)


// --------------- EVENT registers ---------------

//                 *** EVENT 0 ***

LPC_SCT->EV[ SCT_EVENT_0 ].STATE = ENABLE_STATE0;
/* Event 0 only happens in state 0 */


LPC_SCT->EV[ SCT_EVENT_0 ].CTRL =
   SCT_OUTSEL_L       // inputs
 | (0 << 6 )          // CTIN0
 | SCT_IOCOND_RAISE
 | SCT_COMBMODE_IO    // only CTIN0
 | SCT_STATELD_0      // no state changes are allowed
 | SCT_STATEEV_0
 ;

LPC_SCT->START_U = SCT_EVT_0;
// EV0 starts the timer

LPC_SCT->OUT[ SCT_OUTPUT_0 ].CLR = SCT_EVT_0;
// EV0 clear the output

//                  *** EVENT 1 ***

LPC_SCT->EV[ SCT_EVENT_1 ].STATE = ENABLE_STATE0;
// EVT1 habilitado en ST0

LPC_SCT->EV[ SCT_EVENT_1 ].CTRL =
   SCT_EVECTRL_MATCH0 // match
 | SCT_COMBMODE_MATCH // only match
 | SCT_STATELD_0      // state changes are not allowed
 | SCT_STATEEV_0
 ;

Chip_SCT_SetMatchCount( LPC_SCT, SCT_MATCH_0, 250 );
Chip_SCT_SetMatchReload( LPC_SCT, SCT_MATCH_0, 250 );

LPC_SCT->STOP_U = SCT_EVT_1;
// EV1 stops the timer


LPC_SCT->OUT[ SCT_OUTPUT_0 ].SET = SCT_EVT_1;
// EV1 sets the output


//Chip_SCT_ClearControl( LPC_SCT, SCT_CTRL_HALT_L );
LPC_SCT->CTRL_U &= ~( 4 );

}