Content originally posted in LPCWare by Pacman on Mon Oct 06 21:45:55 MST 2014
If you want to go beyond 400MHz, the microcontroller will cost a lot more.
This is because the 28nm will go up to 400MHz, but of course if you're speaking about 10nm technology, you'll be able to get past the 400MHz limit. ;)
-We'll need to keep the price of the M7 below the A5 too. :)
I'm pretty confident that you would be able to do 400M memory operations per second with the 400MHz Cortex-M7, because it has a dual ALU.
SRAM: Agree: More SRAM. 512kB if possible - and contigous. I don't care about Flash memory, as long as there's more than 8kB.
Flash memory isn't really important for me.
It's possible to run high-speed subroutines from SRAM; which is impossible to do in Flash, due to the delay.
So 3MB Flash memory is way over my needs (I don't need to install Windows or put uncompressed pictures in there).
I'd prefer having 8kB Flash and then 256kB or 512kB SRAM compared to 4MB Flash and 240kB SRAM.
-Because I can always interface external memory (such as SPI, SPIFI, SD/MMC, NAND or NOR) without losing much speed.
The speed will be gained back when copying a routine to SRAM temporarily and throwing it away after use.
Note: I'm not saying that there should be no Flash memory at all. I'm just emphasizing how important SRAM is to me.
I would not mind having 128kB Flash memory or more.
DACS: Agree, but I'd prefer 6 of them.
And as JohnR says ... SGPIO should have an option for lsb/msb first, plus an extra option for byte-reversing (4 combinations)
(perhaps being able to control each SGPIO line's bit stream individually, in order to allow multiple interface types at the same time)
Enhanced DMA would be real cool [eg. repeat-count with interleave-increment for each transfer on both source and destination, so you wouldn't have to have 500+ LLIs], but as this is ARM's technology, it's ARM that needs to enhance it.
Yes, and dual logical (AND/OR/XOR) operations on each DMA transfer too one for first transfer, one for next N transfers and one for the last transfer - on both source and destination - I know, I know, I'm asking for too much here.
