Hello,
According to the cortex-M33 documentation, https://developer.arm.com/documentation/100235/0004/the-cortex-m33-processor/exception-model/interru... interrupt preemption is controlled via interrupt priority grouping. I don't see any mention of this in the LPC5502 user manual or datasheet. Is interrupt preemption possible on the LPC5502?
Thanks
Hello,
The interrupt priority register is ARM private peripherals bus, you can also check UM11424 ->
Table 9. Register overview: NVIC (base address = 0xe000e100)
BR
Alice