LPC54618 WWDG clock is not precise?

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LPC54618 WWDG clock is not precise?

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844 Views
Xiaoyh
Contributor III

       I use NXP LPC54618 sdk to test wwdog ,I find that the wwdog is not precise ? When I set wwdog window value is 1s ,but it seems like 800 ms feed dog once?

   my code :

      

void delayWwdtWindow(void)
{
/* For the TV counter register value will decrease after feed watch dog,
* we can use it to as delay. But in user scene, user need feed watch dog
* in the time period after enter Window but before warning intterupt.
*/
while (WWDT->TV > WWDT->WINDOW)
{
__NOP();
}
}

/*!
* @brief Main function
*/
int main(void)
{
wwdt_config_t config;
uint32_t wdtFreq;
bool timeOutResetEnable;

/* Init hardware*/
CLOCK_EnableClock(kCLOCK_Gpio0);
CLOCK_EnableClock(kCLOCK_Gpio2);
/* attach 12 MHz clock to FLEXCOMM0 (debug console) */
CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);

BOARD_InitPins(); //2_2 LED3
BOARD_BootClockPLL180M();
BOARD_InitDebugConsole();

/* Set Red LED to initially be high */
APP_LED_INIT;

#if !defined(FSL_FEATURE_WWDT_HAS_NO_PDCFG) || (!FSL_FEATURE_WWDT_HAS_NO_PDCFG)
POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC);
#endif

/* Enable the WWDT time out to reset the CPU. */
timeOutResetEnable = true;

/* Check if reset is due to Watchdog */
if (WWDT_GetStatusFlags(WWDT) & kWWDT_TimeoutFlag)
{
APP_LED_ON;
PRINTF("Watchdog reset occurred\r\n");
timeOutResetEnable = false;
/* The timeout flag can only clear when and after wwdt intial. */
}

/* wdog refresh test in window mode/timeout reset */
PRINTF("\r\n--- %s test start ---\r\n", (timeOutResetEnable) ? "Time out reset" : "Window mode refresh");

/* The WDT divides the input frequency into it by 4 */
wdtFreq = WDT_CLK_FREQ / 4;

WWDT_GetDefaultConfig(&config);

/*
* Set watchdog feed time constant to approximately 4s
* Set watchdog warning time to 512 ticks after feed time constant
* Set watchdog window time to 1s
*/
config.timeoutValue = wdtFreq * 4 ;
config.warningValue = 512;
config.windowValue = wdtFreq * 1;
/* Configure WWDT to reset on timeout */
config.enableWatchdogReset = true;
/* Setup watchdog clock frequency(Hz). */
config.clockFreq_Hz = WDT_CLK_FREQ;
WWDT_Init(WWDT, &config);

// NVIC_EnableIRQ(APP_WDT_IRQn);

while (1)
{
if (timeOutResetEnable)
{
/* SDK_DelayAtLeastUs can be replaced by Detail User code*/
SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
}
else
{
/* The WINDOW register determines the highest TV value allowed when a watchdog feed is
* performed. If a feed sequence occurs when TV is greater than the value in WINDOW, a
* watchdog event will occur. User can set window same as timeout value if required. */
delayWwdtWindow();
WWDT_Refresh(WWDT);
APP_LED_TOGGLE;   //use a oscilloscope to check time if precise
// PRINTF(" WDOG has been refreshed!\r\n");
/* SDK_DelayAtLeastUs can be replaced by Detail User code*/
// SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
}
}
}

  2400MS   is    NOT  3S2400MS is NOT 3S     

                                                                                                                     thank you!

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829 Views
xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Yang,

The error is normal, because the watchdog internal clock wdt_clk is inaccurate.

BR

XiangJun Rong

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3 Replies
839 Views
xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Yang

Pls refer to section 7.5.79 Watchdog oscillator control register, the wdt_clk is of +/- 40% accuracy over temperature, voltage, and silicon processing variations. So it can explain  that you see 800ms when you expect 1s.

Hope it can help you

BR

XiangJun Rong

 

7.5.79 Watchdog oscillator control register
This register controls the frequency of the watchdog oscillator, in the range of 6 kHz to 1.5
MHz. This oscillator is connected to the watchdog timer and the Micro-tick Timer. The
low-power nature of this oscillator limits its accuracy to +/- 40% over temperature, voltage,
and silicon processing variations. The actual frequency may be measured using the
frequency measure block. See Section 7.2.3.

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Xiaoyh
Contributor III

Thank you for your reply ! As you said ,the error is normal?

                                                                                                                THANK YOU! 

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830 Views
xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Yang,

The error is normal, because the watchdog internal clock wdt_clk is inaccurate.

BR

XiangJun Rong

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