LPC54608 TTL CMOS input pin

[実奥山]

LPC54xxx.pdf has the following description

PIO0_23
[4]5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.

PIO3_18
[2] 5 V tolerant pad with programmable glitch filter (5 V tolerant if VDD present; if VDD not present, do not exceed 3.6 V); provides digital I/O functions with TTL levels and hysteresis; normal drive strength. See Figure 43. Pulse width of spikes or glitches suppressed by input filter is from 3 ns to 16 ns (simulated value).

Does this description indicate that PIO3_18 can input TTL signal?

Can PIO3_18 distinguish between H and L of CMOS and TTL?

PIO0_23 can distinguish between H and L of CMOS, but can't distinguish between H and L of TTL?

[xiangjun_rong]

Hi, 実奥山 ,

For the digital input voltage, the processor do not care about whether it is CMOS or TTL logic, pls refer to following section pin characteristics in data sheet of LPC546xx

The logic voltage is dependent on the VDD voltage, the voltage which is regarded as logic 1 is from 1.5V to 5V with the condition 1.71V<VDD<2.7V, the voltage which is regarded as logic 1 is from 2.0V to 5V with the condition 2.7V<VDD<3.6V.

The logic voltage is dependent on the VDD voltage, the voltage which is regarded as logic 0 is from -0.5V to 0.4V with the condition 1.71V<VDD<2.7V, the voltage which is regarded as logic 0 is from -0.5V to 0.8V with the condition 2.7V<VDD<3.6V.

Hope it can help you

BR

XiangJun Rong