LPC43xx default pins in output mode

[lpcware]

Content originally posted in LPCWare by acristescu on Tue May 08 07:50:52 MST 2012
I am currently designing a board with LPC4330. I have observed that some of the pins have as function #0 (default function) output states. The pins are the followings (on my TQFP144 package):

- P4_7 -> LCD_DCLK
- PF_4 -> SSP1_CLK
- CLK0 -> EMC_CLK0
- CLK2 -> EMC_CLK3

My questions are:

1) Are these really outputs after reset?
2) What are the waveforms or logic states after reset?
3) During reset they are Hiz or outputs?

Thanks for help.

[lpcware]

Content originally posted in LPCWare by acristescu on Mon May 14 02:11:13 MST 2012
Thanks Phil for help.
I am using P4_7 and PF_4 in my schematic for some synchronization signals (IO) but I prefer them to be Hiz at boot (GPIO IN). My design will boot from SPIFI, will not use SSP1. Unfortunately I do not have a board in my hand to check these two pin signals with oscilloscope when LPC43xx boots from SPIFI. Is there any bootloader code published to take a look there?

Thanks.

[lpcware]

Content originally posted in LPCWare by PhilYoung on Sun May 13 00:32:35 MST 2012
the pins should be outputs.
reset is a bit misleading since the boot loader always runs after reset, so don't assume that a pin takes its HW reset value, for many they will have the value set by  the boot loader which has to enable the memory interface to check for an image in external flash depending on the boot mode pins.