LPC43S70 SPIFI XIP and runtime erase

[robberpen]

Hi

I get unexpected hardfault on default periph_flashiap project

1. Traced the source code. I found it trapped on main->Chip_IAP_ReadPID()…->iap_entry()
   Then finally the PC counter point to 0x10400100 which mapping to ROM.(AFAIK)
   However, while dump memory 0x10400100, it get value 0x12345678??? Is it normal?
2. I boot from SPIFI flash(0x14000000), No idea is it possible XIP in SPIFI  and erasing unused block/page simultaneously.

Chip LPC43S70.

Thanks
Peter

R

[Alice_Yang]

Hello @robberpen 

1) For lpc43s70 (flashless part), can not use this API to read PID.  Because on the LPC43x0 microcontrollers, the IAP API is not present.

Work-around:
Use the ISP interface to identify the part ID externally (via the UART) or read the first word
of the part ID directly from OTP memory at location 0x4004 5000. On flashless parts, the
second word of the part ID is always 0.

2) "is it possible XIP in SPIFI  and erasing unused block/page simultaneously."

->> No. When run code in external flash, do not allow erase at the same time. You can put the erase code in RAM. After erase, then XIP to run.

BR

Alice

[robberpen]

Hi Alice

2) "is it possible XIP in SPIFI  and erasing unused block/page simultaneously."

->> No. When run code in external flash, do not allow erase at the same time. You can put the erase code in RAM. After erase, then XIP to run.

That is means, I should modified part of "erase code" from linker script maping from XIP to RAM or entire ".text" section to RAM?

Regards
Peter

[frank_m]

This depends on your setup, but only the code involved in erasing/programming must run from RAM.
Flash does not allow read or fetch access during programming, for technical reasons.
This applies to internal Flash as well, especially MCUs with only one Flash bank - which applies to the majority of devices.

[robberpen]

Thank your reply, I will try to research in advance.

Based on your comments about flash bank, how if flash type is 2 banks, then XIP in bank0, runtime erase/write data to bank1?

[frank_m]

The flashing process (tunneling charges onto the isolated gate, or removing them) requires a voltage of >9V, which is usually generated on-chip (via charge pumps). Which is the reason why a read/fetch is not possible in this state.

Each "bank" usually has it's own charge pump, i.e. can be set to programming mode / voltage individually. All sectors in one bank can only be set to programming mode at once, obviously. This problem remains the same for external flash with parallel or serial interfaces, and for internal Flash on MCUs. Multiple banks are thus increased expense, and make the chip more expensive.

Problem is, this terminology is (was ?) not always consistent amongst different vendors.

The datasheet of your flash device should state if and how read access during programming is possible, even if not going into details about the internal configuration.