LPC4357 clock configuration

[quyenngo]

Hi all,

I have a question about clock configuration.

LPC43xx user manual document say that:

  The following procedure shows how to change the default setting of the core clock
(BASE_M4_CLK = 96 MHz; IRC = PLL1 clock source) to an operating frequency above
110 MHz while also changing the clock source from IRC to crystal oscillator:
1. Select the IRC as BASE_M4_CLK source.
2. Enable the crystal oscillator (see Table 127
).
3. Wait 250 s.
4. Reconfigure PLL1 as follows (see Table 138
):
– Select the M and N divider values to produce the final desired PLL1 output
frequency f
.
– Select the crystal oscillator as clock source for PLL1.
outPLL
5. Wait for the PLL1 to lock.
6. Set the PLL1 P-divider to divide by 2 (DIRECT = 0, PSEL=0).
7. Select PLL1 as BASE_M4_CLK source. The BASE_M4_CLK now operates in the
mid-frequency range.
8. Wait 50 s.
9. Set the PLL1 P-divider to direct output mode (DIRECT = 1).
The BASE_M4_CLK now operates in the high-frequency range.

In step 5. Wait for the PLL1 to lock, what is the maximum time system can wait, and what will system do if the PPL1 is unstable for a long time?

Thank you and best regards.

[quyenngo]

Thank you so much jeremyzhou,

Another question, in the lpc4357_oem_board library, when configure clock, it not check the PLL1 lock status follow the above procedure (step 5: Wait for PLL1 to lock). But the clock is still working well, how they do that?

Very best regards.

[jeremyzhou · Accepted solution]

Hi Quyen Ngo,

The PLL setting process can be completed in 100us, and definitely the MCU can't work properly if the system clock become unstable.
Have a great day,
Ping

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