LPC4337 Flash Bank B can not be programmed

[lpcware]

Content originally posted in LPCWare by Alex on Wed Feb 06 01:58:39 MST 2013
Hi,

I'm currently trying to set up a dual core application on the LPC4337. The M4 code will be stored in Flash Bank A and the M0 code in Flash Bank B.

I'm using JLink and IAR EWARM 6.5 to flash and debug the applications.

The M4 code can be flashed without any problems but the M0 code can not be written to Flash Bank B. The JLINK driver reports verification errors after flashing. There is one strange thing: The debugger says "Core is locked up!" when flashing the M0 project. Maybe this is the cause?

Then I tried Segger JFlash. The same here writing to Bank B is not possible. Reading the Bank is no problem.

Or possibly the JLINK debugger probe is too old? It is version 6.0 from 2009...

Here is what the IAR debugger says:
Wed Feb 06, 2013 09:55:02: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\config\flashloader\NXP\FlashNXPLPC18xx.mac
Wed Feb 06, 2013 09:55:09: JLINK command: ProjectFile = C:\Users\.........\Software\NXP_TRAINING\M0_src\settings\NXPTrainingM0_Debug.jlink, return = 0
Wed Feb 06, 2013 09:55:09: JLINK command: scriptfile = C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\config\debugger\NXP\LPC4350_DebugCortexM0.JLinkScript, return = 0
Wed Feb 06, 2013 09:55:09: Device "LPC4337_M0" selected (0 KB flash, 0 KB RAM).
Wed Feb 06, 2013 09:55:09: DLL version: V4.62a, compiled Feb  4 2013 11:51:03
Wed Feb 06, 2013 09:55:09: Firmware: J-Link ARM V6 compiled Jun 20 2012 19:43:26
Wed Feb 06, 2013 09:55:09: JTAG speed is initially set to: 32 kHz
Wed Feb 06, 2013 09:55:09: NXP LPC4350 (Cortex-M4+M0 core) J-Link script
Wed Feb 06, 2013 09:55:09: TotalIRLen = 8, IRPrint = 0x0011
Wed Feb 06, 2013 09:55:09: TotalIRLen = 8, IRPrint = 0x0011
Wed Feb 06, 2013 09:55:09: Found Cortex-M0 r0p0, Little endian.
Wed Feb 06, 2013 09:55:09: FPUnit: 2 code (BP) slots and 0 literal slots
Wed Feb 06, 2013 09:55:11: J-Link script: Performing reset sequence
Wed Feb 06, 2013 09:55:11: Core is locked-up!
Wed Feb 06, 2013 09:55:11: CPU halted
Wed Feb 06, 2013 09:55:11: Hardware reset with strategy 0 was performed
Wed Feb 06, 2013 09:55:11: Initial reset was performed
Wed Feb 06, 2013 09:55:11: Found 2 JTAG devices, Total IRLen = 8:
Wed Feb 06, 2013 09:55:11:  #0 Id: 0x4BA00477, IRLen:  4, IRPrint: 0x1 CoreSight JTAG-DP
Wed Feb 06, 2013 09:55:11:  #1 Id: 0x0BA01477, IRLen:  4, IRPrint: 0x1 CoreSight SW-DP
Wed Feb 06, 2013 09:55:11: ------- Prepare for flashloader -------
Wed Feb 06, 2013 09:55:11: 1504 bytes downloaded and verified (5.54 Kbytes/sec)
Wed Feb 06, 2013 09:55:11: Loaded debugee: C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\config\flashloader\NXP\FlashNXPLPC18xx_RAM40K.out
Wed Feb 06, 2013 09:55:11: Target reset
Wed Feb 06, 2013 09:55:12: Core is locked-up!
Wed Feb 06, 2013 09:55:12: CPU halted
Wed Feb 06, 2013 09:55:12: Downloaded C:\Users\.........\Software\NXP_TRAINING\M0_src\Debug\Exe\cpp.out to flash memory.
Wed Feb 06, 2013 09:55:12: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\config\debugger\NXP\Trace_LPC18xx_LPC43xx.dmac
Wed Feb 06, 2013 09:55:12: J-Link script: Performing reset sequence
Wed Feb 06, 2013 09:55:12: Hardware reset with strategy 0 was performed
Wed Feb 06, 2013 09:55:12: 4960 bytes downloaded into FLASH and verified (4.19 Kbytes/sec)
Wed Feb 06, 2013 09:55:12: Warning: 
Verify error at address 0x1B000000, target byte: 0xFF, byte in file: 0x08
Wed Feb 06, 2013 09:55:12: Warning: 
Verify error at address 0x1B000001, target byte: 0xFF, byte in file: 0x20

Best regards,
Alex

[lpcware]

Content originally posted in LPCWare by iaun.hma67 on Tue Oct 06 01:55:02 MST 2015
hello
I am a beginner in lpc4337 and trying to make a project by this processor...
I want to blink the LEDs connected to P6.9 & P6.10 with core M0 and blink the other tow LEDs connected to P6.11 & P6.12 with coreM4.
I am working by keil 5 and registers without using of CMSIS standard function. my programmer is j_link and I have work on OPEN18xx/43xxB1 training board(fabricated by Wave Share).
by using your post and others I don't understand how to configure my program :((
I write this code for core M0 :

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
#include <LPC43xx.h>

void delay_ms(int Del)
{
long int i;
for(i=0;i<Del*8000;i++);
}
int main(void)
{

//LED4 P6.9   GPIO3[5]  FUNC0
LPC_SCU->SFSP6_9=0x00000028;
LPC_GPIO_PORT->DIR[3] |= (1 <<5);
  //LED3 P6.10  GPIO3[6]  FUNC0 
LPC_SCU->SFSP6_10=0x00000028;
LPC_GPIO_PORT->DIR[3] |= (1 <<6);
while (1)
{                          
LPC_GPIO_PORT->SET[3]=1<<5;       // GPIO3[5] :   (LED D4)
delay_ms(500);
LPC_GPIO_PORT->SET[3]=1<<6;       // GPIO3[6] :   (LED D3)
delay_ms(500);
LPC_GPIO_PORT->CLR[3]=1<<5;       // GPIO3[5] :   (LED D4)
delay_ms(500);
LPC_GPIO_PORT->CLR[3]=1<<6;       // GPIO3[6] :   (LED D3)
delay_ms(500);
}
}

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
and setting for M0 core like this:

image1

image2

image3

image4

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

and this code for core M4 in the other project:

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////  
#include <LPC43xx.h>

void delay_ms(int Del)
{
long int i;
for(i=0;i<Del*8000;i++);
}

/* Boot the M0 core */
void lpc43xx_m0_boot(void)
{
/* Make sure the M0 core is being held in reset via the RGU */
LPC_RGU->RESET_CTRL1 = (1 << 24);
}



int main(void)
{


//LED2 P6.11  GPIO3[7]  FUNC0
LPC_SCU->SFSP6_11=0x00000028;
LPC_GPIO_PORT->DIR[3] |= (1 <<7);
//LED1 P6.12  GPIO2[8]  FUNC0
LPC_SCU->SFSP6_12=0x00000028;
LPC_GPIO_PORT->DIR[2] |= (1 <<8);

while (1)
{                          
LPC_GPIO_PORT->SET[3]=1<<7;       // GPIO3[7] :   (LED D2)
delay_ms(1000);
LPC_GPIO_PORT->SET[2]=1<<8;       // GPIO2[8] :   (LED D1)
delay_ms(1000);
LPC_GPIO_PORT->CLR[3]=1<<7;       // GPIO3[7] :   (LED D2)
delay_ms(1000);
LPC_GPIO_PORT->CLR[2]=1<<8;       // GPIO2[8] :   (LED D1)
delay_ms(1000);

}
}

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
and setting for M0 core like this:

image5

image6

image7

image8

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
i should say that i use wizard project in keil 5 to make these tow project  & i want to run all of these project by using any new heeder file or lib :~
i want to do all the necessary work like releasing M0 core from reset just by basic registers.
i read all of corresponsive post in this site and in internet, but i just confused !!!
thank you for attention

[lpcware]

Content originally posted in LPCWare by Alex on Fri Feb 08 01:13:02 MST 2013
Oh, I was not aware that the debugger will use the M0 core. Right, this may be the reason.

[lpcware]

Content originally posted in LPCWare by bavarian on Thu Feb 07 11:11:18 MST 2013
You seem to use the M0 core to program the flash. This is possible, but after reset the M= is in reset, the M4 is running.
Somebody, the M4 or the debugger by means of a script needs to take the M0 out of reset before it can be used to do something.

Maybe the debugger is doing it (I don't the .mac file which is used), but there are some other reasons why it could fail.
The best thing is normally, to take for programming of the flash always the M4 core (selection in the Debugger settings of your project).


Hope this helps,
Bernhard.

[lpcware]

Content originally posted in LPCWare by Alex on Wed Feb 06 04:11:59 MST 2013
Fixed it by myself.

It seems as if the JTAG frequency or the CPU frequency was not set correctly in the JLINK/ JFLASH project file.

I set the JTAG initialization frequency to 5 kHz and the CPU frequency to auto or to 200 MHz (operating frequency while CPU is running).

Now it works fine.

But what I don't understand is why Bank A could be programmed...

Regards
Alex