Reading Chapter 19 (SSP ...) of the User Manual, my understanding of the usage is that I should configure to use SSP0 (say) as SPI, and then use code similar to this:
void SSP_SPI_SR(uint16_t* sendBuffer, uint16_t* recvBuffer, uint8_t length)
{
uint8 len1 = length, len2 = length;
// Ensure SSP receive FIFO is empty (by reading data out of it if necessary)
while(SSP0SR & RNE) SSP0DR;
IOCLR0 = 0x00100000; // SSEL active (down)
while(len1 || len2)
{
if (len1 && (SSP0SR & TNF)) // Data to send and transmit FIFO isn’t full?
{
SSPODR = *sendBuffer++;
len1--;
//
// add a wait loop here if need to prevent buffer underrun at slave
}
if (len2 && (SSP0SR & RNE)) // Data to receive and receive FIFO has data available
{
*recvBuffer++ = SSP0DR;
len2--;
}
}
}
IOSET0 = 0x00100000; // SSEL inactive (up)
}
// Usage :
uint16_t pollSequence[9] = {0xEBEB, 0xEBEB, 0xEBEB,
0xEBEB, 0xEBEB, 0xEBEB,
0xEBEB, 0xEBEB, 0xFFFF};
uint16_t pollReplies[9] = {0};
SSP_SPI_SR(pollSequence, pollReplies, 9);
Is that right?
If so I'm puzzled! Using CPOL=1, CPHA=0. Section 19.5.2.4 explicitly says:
However, in the case of continuous back-to-back transmissions, the SSEL signal must be
pulsed HIGH between each data word transfer. This is because the slave select pin
freezes the data in its serial peripheral register and does not allow it to be altered if the
CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave
device between each data transfer to enable the serial peripheral data write. On
completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK
period after the last bit has been captured.
But given that the FIFO is being used for data transmission, I don't understand how I am supposed to toggle *SSEL between transfers.
Help greatly appreciated.
Thanks, David
