LPC1778 seems like not recognizing the SRAM MSB address

[lpcware]

Content originally posted in LPCWare by arion2001 on Wed Feb 25 00:18:55 MST 2015
Hi,

I am doing some read write test on my SRAM hooking up to LPC as shown in the attached image. So I am getting some pretty strange result. It seems like those page override or memory aliasing kind of thing. The debugger seems to be showing that after every 1MB there is a repeated copy of the information I wrote into the SRAM. I understand that the upper limit of the memory should be defined as 0x980FFFFF instead of 0x98100000 so I introduced a condition in the this portion of the code.

How I defined my pins(OEN pin is correct by the way)

#include <LPC177x_8x.h>
void FLASH_Autoselect(void);
void Flash_CFI(void);
unsigned char Flash_Read(unsigned long Source_Address);
unsigned char EMC_Write(unsigned short DQ_In, unsigned long Target_Address);
unsigned char EMC_Read(unsigned short *DQ_Out, unsigned long Source_Address);
unsigned char Flash_SinWord_Prog(unsigned long Target_Address);
unsigned char NOR_Sec_Erase(unsigned long Target_Address);
int NewmemTest(void);
void Memtest(void);
unsigned char EMC_Write_Long(unsigned long DQ_In, unsigned long Target_Address);
unsigned char SRAM_Testwrite(unsigned long DQ_In, unsigned long Target_Address);
void SRAM_Init(void);

#define SRAM_OnChip_BaseAddr       0x10000000 
#define SRAM_OnChip_EndAddr        0x1000FFFF
#define Flash0_BaseAddr            0x80000000   
#define Flash0_EndAddr             0x80FFFFFF 
#define Flash1_BaseAddr            0x81000000
#define Flash1_EndAddr             0x81FFFFFF
#define SRAM0_BaseAddr             0x98000000 
#define SRAM0_EndAddr              0x980FFFFF 
#define SRAM1_BaseAddr             0x9C000000 
#define SRAM1_EndAddr              0x9C0FFFFF 

#define WRITE_COMPLETE               0
#define WRITE_ABORT                  1
#define TIME_OUT                     2
#define WRITE_SUSPEND                3
#define WRITE_NOT_COMPLETE           4
#define INVALID_ADDRESS              5

//EMC_CS2 SRAM
//P2[14]
#define SRAM_CS2_SEL          LPC_IOCON->P2_14 |= 0x31

//EMC_OEN Shared
//P4[24]
#define OEN_SEL               LPC_IOCON->P4_24 |= 0x31

//EMC_WEN Shared
//P4[25]
#define WEN_SEL                   LPC_IOCON->P4_25 |= 0x31

//EMC_BLS0 SRAM Lower Byte
//P4[26]
#define SRAM_BLS0_SEL            LPC_IOCON->P4_26 |= 0x31

//EMC_BLS1 SRAM Upper Byte
//P4[27]
#define SRAM_BLS1_SEL          LPC_IOCON->P4_27 |= 0x31

//Nor_Flash /CS0 pin4[30]
#define NORFLASH_CS0_SELLPC_IOCON->P4_30 |= 0x31

//Nor_Flash /CS1 pin4[31]
#define NORFLASH_CS1_SELLPC_IOCON->P4_31 |= 0x31

//Nor_Flash RY/BY pin0[4]
//Ready Busy indicates running in progress. At High Z = ready, at Vil = actively erasing/programming
#define NORFLASH_RYBY_SEL      LPC_IOCON->P0_4   |= 0x218 
#define NORFLASH_RYBY_IN       LPC_GPIO4->DIR &= ~(0x10)
#define NORFLASH_RYBY_BIT      LPC_GPIO4->PIN &    0x10

static void pinConfig_EMC(void) {
//Select slew rate and also config for EMC use = 0x31 , with pullup
LPC_IOCON->P3_0 |= 0x31; // D0 @ P3.0 
LPC_IOCON->P3_1 |= 0x31; // D1 @ P3.1 
LPC_IOCON->P3_2 |= 0x31; // D2 @ P3.2 
LPC_IOCON->P3_3 |= 0x31; // D3 @ P3.3 

LPC_IOCON->P3_4 |= 0x31; // D4 @ P3.4 
LPC_IOCON->P3_5 |= 0x31; // D5 @ P3.5 
LPC_IOCON->P3_6 |= 0x31; // D6 @ P3.6 
LPC_IOCON->P3_7 |= 0x31; // D7 @ P3.7 

LPC_IOCON->P3_8 |= 0x31; //D8 @ P3.8 
LPC_IOCON->P3_9 |= 0x31; // D9 @ P3.9 
LPC_IOCON->P3_10 |= 0x31; // D10 @ P3.10 
LPC_IOCON->P3_11 |= 0x31; // D11 @ P3.11 

LPC_IOCON->P3_12 |= 0x31; // D12 @ P3.12 
LPC_IOCON->P3_13 |= 0x31; // D13 @ P3.13 
LPC_IOCON->P3_14 |= 0x31; // D14 @ P3.14 
LPC_IOCON->P3_15 |= 0x31; // D15 @ P3.15  //also  A-1 LSB address input in byte mode

//LPC_IOCON->P4_0 |= 0x31; // A0 @ P4.0    //added in to mimic code, temporary not used
LPC_IOCON->P4_1 |= 0x31; // A1 @ P4.1 
LPC_IOCON->P4_2 |= 0x31; // A2 @ P4.2 
LPC_IOCON->P4_3 |= 0x31; // A3 @ P4.3 

LPC_IOCON->P4_4 |= 0x31; // A4 @ P4.4 
LPC_IOCON->P4_5 |= 0x31; // A5 @ P4.5 
LPC_IOCON->P4_6 |= 0x31; // A6 @ P4.6 
LPC_IOCON->P4_7 |= 0x31; // A7 @ P4.7 

LPC_IOCON->P4_8 |= 0x31; // A8 @ P4.8 
LPC_IOCON->P4_9 |= 0x31; // A9 @ P4.9 
LPC_IOCON->P4_10 |= 0x31; // A10 @ P4.10 
LPC_IOCON->P4_11 |= 0x31; // A11 @ P4.11 

LPC_IOCON->P4_13 |= 0x31; // A13 @ P4.13 
LPC_IOCON->P4_14 |= 0x31; // A14 @ P4.14 
LPC_IOCON->P4_15 |= 0x31; // A15 @ P4.15 
LPC_IOCON->P4_16 |= 0x31; // A16 @ P4.16 

LPC_IOCON->P4_17 |= 0x31; // A17 @ P4.17 
LPC_IOCON->P4_18 |= 0x31; // A18 @ P4.18 
LPC_IOCON->P4_19 |= 0x31; // A19 @ P4.19 
//LPC_IOCON->P4_20 |= 0x31; // A20 @ P4.20 

//LPC_IOCON->P4_21 |= 0x31; // A21 @ P4.21 
//LPC_IOCON->P4_22 |= 0x31; // A22 @ P4.22 
//LPC_IOCON->P4_23 |= 0x31; // A23 @ P4.23 
//LPC_IOCON->P5_0  |= 0x31; // A24 @ P5.0 
//LPC_IOCON->P5_1  |= 0x31; // A25 @ P5.1 

  //NORFLASH_CS0_SEL;
  //NORFLASH_CS1_SEL;
  //NORFLASH_RYBY_SEL;

  SRAM_CS2_SEL;
  SRAM_BLS0_SEL;
  SRAM_BLS1_SEL;
  OEN_SEL;
  WEN_SEL; 
}

void Memtest(void)
{
  //Remember the end address where CPU and memory does not see A20 pin for SRAM.
  //unsigned short *start= (unsigned short *) 0x98000000UL;   
  unsigned short *start= (unsigned short *) SRAM0_BaseAddr;  
  unsigned short *finish =(unsigned short *)SRAM0_EndAddr; 
  unsigned int value=0;
  unsigned short pattern = 0x5555;
  unsigned short inv_pattern = 0xAAAA;
  unsigned short readback = 0;
  //unsigned int pattern = 0xdead;
  //unsigned int inv_pattern = 0xbeef;
  int i;
  int Memory_Size = 32;
  
  //unsigned long Memory_Size = 1048576;
  
  //int Memory_Size = 1048577;
  //int Memory_Size = 2097152;
  /*for(i = 0; i < Memory_Size; i+= 4)
  //for(i = 0; i < 32; i+= 1)  //try just 32 bytes first.
  {
    *start = value; 
    start++;
    value++;
  }*/
  for(i = 0; i < Memory_Size; i+= 2) //Populate SRAM with pattern
  {
    *start = pattern;
    readback = *start;
    start++;   
    //if(start>finish) //Boundary condition
    // {
    //    break;
    // }
  }
  
   /*for(i = Memory_Size; i > 0; i-= 2)
  {
    *finish = value; 
    finish--;
    
  }*/

}

I understand that the upper limit of the memory should be defined as 0x980FFFFF instead of 0x98100000 so I introduced a condition in the this portion of the code, but I am still seeing it.

void Memtest(void)
{
  //Remember the end address where CPU and memory does not see A20 pin for SRAM.
  //unsigned short *start= (unsigned short *) 0x98000000UL;   
  unsigned short *start  = (unsigned short *)SRAM0_BaseAddr;  //0x98000000 
  unsigned short *finish = (unsigned short *)SRAM0_EndAddr;   //0x980FFFFF 
  unsigned int value  = 0;
  unsigned short pattern = 0x5555;
  unsigned short inv_pattern = 0xAAAA;
  unsigned short readback = 0;
  //unsigned int pattern = 0xdead;
  //unsigned int inv_pattern = 0xbeef;
  int i;
  int Memory_Size = 32;
  
  //unsigned long Memory_Size = 1048576;
  
  
  EMC_Write(pattern, start);
  
}


unsigned char EMC_Write(unsigned short DQ_In, unsigned long Target_Address) //address may need to use unsigned long to address 32 bits length address
{
  
  if(Target_Address >= Flash0_BaseAddr && Target_Address <= SRAM1_EndAddr)
  {
    new_address = (unsigned short *)Target_Address; //the heart of the memory address translation
    *new_address = DQ_In;    
    return 0;
  }
  else
  {
    return INVALID_ADDRESS; //invalid address
  }

}