Content originally posted in LPCWare by sturzi on Tue Apr 07 00:45:29 MST 2015
Hi,
I was hoping someone could help me with this issue. While stress testing the mass storage class on an LPC1769 we found an issue for which we don't have an explanation.
Every now and then (in the order of about 15 minutes) when processing the received data the DV (data valid) bit in the USBRxPlen register is not set (PKT_LNGTH and PKT_RDY however are set as expected). In the user manual it states that for non-isochronous transfers no interrupt is generated if the data isn't valid, therefore it is a bit of a mystery why this happens. It only says that an invalid packet can be generated with a bus reset, but since no bus reset happens this can't be the issue.
If anyone has more information regarding this issue I'd be very interested to hear it.
Thanks
