LPC11c24 controller interrupt vector offset relocation

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LPC11c24 controller interrupt vector offset relocation

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ag00539523
Contributor I

Hi,

Iam working on LPC11C24 micro controller. we are developing a  secondary boot loader by using IAP commands. In bootloader, while jumping to application, we are not able to relocate interrupt vector table.

Application  using CAN_IRQn , EINT1_IRQn, SysTick_IRQn , where as bootloader need to use CAN_IRQn, SysTick_IRQn in the bootloader . Application and bootloader are using same interrupts (CAN_IRQn, SysTick_IRQn). 

I tried by using vector table relocation to RAM as mentioned in some posts,but observed that application interrupts are not working.

Suggest on this.

please find below implementation. My application code starts from 0x3000. RAM starts from 0x10000000.

tried by writing redirecting to RAM code in bootloader code as well as application also. 

#define vector_in_ram  ((uint32_t*)0x10000000)

__disable_irq();

uint8_t i;
uint32_t *p = (uint32_t *) 0x3000;
for(i = 0; i<128; i++)
{
vector_in_ram[i] = *p;
p++;

}
LPC_SYSCON->SYSMEMREMAP = 0x1;


asm volatile("ldr r0, =0x3000");
asm volatile("ldr r0, [r0]");
asm volatile("mov sp, r0");

asm volatile("ldr r0, =0x3004");
asm volatile("ldr r0, [r0]");
asm volatile("mov pc, r0");

Please provide some inputs on this.

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1 Reply

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi Anusha G,

     About the secondary bootloader for LPC11C24, please refer to our application note:

https://www.nxp.com/docs/en/application-note/AN10995.zip 

   Because the LPC11C24 is based on the ARM Cortex-M0 core, it is not like the ARM Cortex-M0+ have the VTOR register to relocate the vector, M0 core don't have it.

   So, you need to associated the code to relocate the vector.

   For the details, please check the application note which I recommend you.

   pastedImage_2.png

Wish it helps you!

If you still have question about it, please kindly let me know.
Have a great day,
Kerry

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