LPC RTC time shifts

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LPC RTC time shifts

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sutton
Contributor III

Anyone have any experience with minimizing RTC shift? I'm using a LPC2148 on an older system,
and for the most part our solution is having an NTP server update the clock every morning.

However, some customers won't put the system on the network. And, some complaints are upwards of
15 minutes per month, which is way out of spec for the crystal we use. So, I did a little research.
We use a 32.768khz crystal with a 20ppm tolerance with the proper capacitors recommended by the
LPC datasheet and user manual, which I think is around 1 minute shift a month, give or take.
So, 15 minutes was way out there.

We have a display on our system, and I noticed that if the RTC time is read continuous and displayed
on the screen, the shift is drastic. If the RTC is read less often (say every 5 minutes), it is
much, much better. What could be the cause of this? Reading the RTC registers (HOURS, MINUTES, SECONDS), which is the recommended way in the user manual, no matter how often, shouldn't have any effect on shift, or should it?

Sutton

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4 Replies

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sutton
Contributor III

I'm guessing that LPC engineers don't monitor this forum.  There is some type of RTC anomaly on the LPC2138/LPC2148 microcontrollers.  If you read the clock continuously, after 4 days, the clock is off 2 mins or more.  If you don't and come back 4 days later, the clock is only off 3 secs or so, which is reasonable.  So, reading the clock does pause the clock in some fashion or otherwise cause severe inaccuracies if you read often.  I wish someone, who knows how the chips work, would chime in and give some feedback on the internal operation of reading the RTC.

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frank_m
Senior Contributor III

As you correctly assume, this question can most probably only answered by NXP engineers knowing internal design details.

However, it makes sense to assume the RTC counter registers might be stopped when reading out. Since you can't read all register values at once, you would get inconsistent results at one of the regular overflow events.

I know of other (and later) designs that use shadow registers which are internally read out at once, and can then be read in sequential manner by the user without corruption.

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diego_charles
NXP TechSupport
NXP TechSupport

Hi @sutton 

I hope you are doing well!

I just wrote you via your internal ticket, I think it relates to the same topic as this thread, correct me if I am wrong.

 All the best, 

Diego.

 

 

 

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784 Views
converse
Senior Contributor V

You could try submitting a support ticket:

https://support.nxp.com/s/

 

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